Method for preparing interface layer of high-k dielectric layer

Abstract

The invention provides a method for preparing the interface layer of a high-K dielectric layer. The method includes the following steps that: first step, a semiconductor silicon substrate is provided; second step, pre-cleaning before high-K dielectric layer deposition is performed on the semiconductor silicon substrate through using an acid tank; third step, in situ steam generation and flash lamp annealing combination or rapid thermal oxidation and flash lamp annealing combination is applied to the growth of the interface layer on the semiconductor silicon substrate; fourth step, the high-K dielectric layer is deposited on the interface layer; and fifth step, after the deposition of the high-k dielectric layer, post high-K annealing is performed on the semiconductor silicon substrate.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, more specifically, the invention relates to a method for preparing an interface layer of a high-K (high dielectric constant) dielectric layer. Background technique [0002] With the rapid development of Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI), the size of MOS devices has been continuously reduced. In order to increase the response speed of the device, increase the driving current and the capacity of the storage capacitor, the thickness of the gate oxide layer in the device is continuously reduced. However, two subsequent problems have become important factors hindering the further development of integrated circuits: leakage and breakdown. When the gate oxide thickness is less than Due to the quantum tunneling effect, carriers can flow through this ultra-thin gate dielectric, and the probability of carrier tunneling increases exponentially with the...

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Problems solved by technology

[0009] Since the high-K gate dielectric material is mainly metal oxide, there must be oxygen in the preparation process, and the reaction between oxygen and silicon will form silicon dioxide or silicide between the high-K dielectric layer and the silicon substrate. Interface oxide layer, due to the existence of the oxide layer, the reduction of the equivalent oxide thickness (EOT) becomes difficult

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