Fan-out package structure and manufacturing method thereof

Abstract

The invention provides a fan-out package structure and a manufacturing method thereof. The structure comprises a chip having electrodes. The active surface of the chip is upward; the chip is circumferentially filled with a first insulating resin layer; the top portion of the first insulating resin layer is higher than the upper surface of the chip; the chip and the top portion of the first insulating resin layer are covered by a second insulating resin layer; the surface of the second insulating resin layer is provided with a re-wiring layer which is connected with the electrodes of the chip through openings of the second insulating resin layer; the second insulating resin layer and the re-wiring layer are covered by a third insulating resin layer; the third insulating resin layer is provided with openings for exposing bonding pads of the re-wiring layer; the bonding pads of the re-wiring layer are connected with conductive columns; the conductive columns are electrically connected with the electrodes on the active surface of the chip through the re-wiring layer; and the lower surface of the chip and the bottom of the first insulating resin layer are provided with a protection layer. The package structure does not have a bearing piece, thereby helping to reduce package thickness, and meanwhile, enlarging application range of the technology; and copper columns are not prepared on the chip, thereby facilitating to reduce the cost.

Description

technical field [0001] The invention relates to a fan-out package (FOWLP) structure and a manufacturing method, belonging to the technical field of integrated circuit chip packaging. Background technique [0002] With the trend of multi-function and miniaturization of electronic products, high-density microelectronic assembly technology has gradually become the mainstream in the new generation of electronic products. In order to cope with the development of a new generation of electronic products, especially the development of smart phones, PDAs, ultrabooks and other products, the size of chips is developing in the direction of higher density, faster speed, smaller size, and lower cost. The emergence of fan-out wafer-level packaging technology (Fanout Wafer Level Package, FOWLP) has satisfied the characteristics of thinner chip products and saving materials (package substrates), but how to reduce the cost of fan-out wafer-level packaging products has become a need for resear...

AI Technical Summary

Problems solved by technology

[0009] The disadvantage of this technology is that the first insulating resin layer is coated in the third step of the process. Since the thickness of the chip is usually more than 50 microns, the thickness of the coated insulating resin is not easy to control, which is not conducive to the production of fine lines.

[0011] The disadvantage of this technology is that it needs a substrate as a carrier, which increases the complexity of the process and is not conducive to the reduction of the overall thickness of the chip.

Although this technology avoids the use of the second carrier board, the production of copper pillars, the grinding and polishing of the plastic sealing layer, and the control of the outcropping of copper pillars make this technology very expensive

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