Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Packaging structure and manufacturing method for redistribution leading wire layer

A technology for redistribution leads and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., can solve the problems of complex manufacturing process of redistribution lead layer, insufficient environmental protection, low production efficiency, etc., and achieve reduction in process Complexity, avoidance of risk of damage, effect of saving material

Active Publication Date: 2015-12-09
SJ SEMICON JIANGYIN CORP
View PDF7 Cites 19 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a packaging structure and a method for manufacturing a redistribution lead layer, which is used to solve the problem of complex manufacturing process and low production efficiency of the redistribution lead layer in the prior art. The problem of not being environmentally friendly

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Packaging structure and manufacturing method for redistribution leading wire layer
  • Packaging structure and manufacturing method for redistribution leading wire layer
  • Packaging structure and manufacturing method for redistribution leading wire layer

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0067] The present invention provides a manufacturing method of redistribution lead layer, please refer to figure 1 , shown as a process flow diagram of the method, comprising the following steps:

[0068] S1: providing a carrier, forming an adhesive layer on the surface of the carrier;

[0069] S2: Paste at least one chip on the adhesive layer, wherein the chip faces upward;

[0070] S3: forming a plastic encapsulation layer covering the chip on the surface of the carrier;

[0071] S4: Forming several through holes corresponding to the electrical leads of the chip in the plastic encapsulation layer by laser etching;

[0072] S5: Depositing metal in the through hole and on the surface of the plastic encapsulation layer to obtain a redistribution wiring layer.

[0073] See first figure 2 , performing step S1: providing a carrier 1, and forming an adhesive layer 2 on the surface of the carrier 1.

[0074] Specifically, the function of the carrier 1 is to provide a rigid st...

Embodiment 2

[0098] This embodiment adopts basically the same technical solution as Embodiment 1. The difference is that in Embodiment 1, only laser etching is used to form through holes in the plastic packaging layer, and finally the metal lines of the redistribution lead layer are formed in the plastic packaging layer. In this embodiment, the redistribution lead layer pattern (including through holes and metal circuit patterns) is formed in the plastic encapsulation layer by laser etching, and then the metal deposition process is used to form the redistribution lead layer composed of metal and metal lines in the through holes. The lead layer is distributed, and finally the metal circuit of the redistributed lead layer is embedded in the plastic sealing layer, which has higher reliability.

[0099] See first Figure 2 to Figure 4 , performing steps S1 to S3 that are basically the same as those in Embodiment 1.

[0100] then see Figure 5 and Figure 12 , performing step S4: using laser...

Embodiment 3

[0119] This embodiment adopts basically the same technical solution as that of Embodiment 2, except that in this embodiment, the redistribution wiring layer is obtained by laser direct forming.

[0120] Laser Direct Structuring (LDS) is a method of creating electronic circuits on injection-molded plastic parts using steps such as laser ablation and metallization. The laser direct molding method usually includes the following steps: (1) Injection molding (Injection molding), which is automatically formed after the molten plastic is sprayed out by a plastic injection machine. (2) Laser Activation (Laser Activation), this step uses the computer to control the movement of the laser according to the trajectory of the conductive pattern, projects the laser onto the molded three-dimensional plastic device, and activates the circuit pattern within a few seconds. In this process, the laser energy breaks the organic coating surrounding the metal particles on the one hand, exposing the m...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a packaging structure and a manufacturing method for a redistribution leading wire layer. The method includes following steps: S1, a carrier is provided, a viscose layer is formed on the surface of the carrier; S2, at least a chip is pasted on the viscose layer, wherein the front surface of the chip is upwardly arranged; S3, a plastic packaging layer covering the chip is formed on the surface of the carrier; S4, a plurality of through holes corresponding to electric lead-out of the chips are formed in the plastic packaging layer by employing a laser etching method; and S5, metal is deposited in the through holes and on the surface of the plastic packaging layer, and the redistribution leading wire layer is obtained. According to the packaging structure and the manufacturing method, the laser etching method is employed to replace steps of photoetching and etching of the through holes and metal lines, the process complexity is greatly reduced, the front surface of the chip is exposed and a passivation layer is deposited without the planarization step or the stripping of the viscose layer, the redistribution leading wire layer is manufactured directly based on the plastic packaging layer, materials are saved, the method is more environmentally friendly, and the risk of the damage to the front surface of the chip in the process of planarization or stripping the viscose layer can be avoided.

Description

technical field [0001] The invention belongs to the field of semiconductor packaging, and relates to a packaging structure and a manufacturing method of a redistribution lead layer. Background technique [0002] With the rapid growth of the semiconductor industry, in order to further reduce the power consumption of semiconductor devices and improve the operating speed and bandwidth of semiconductor devices, it is necessary to provide more innovative semiconductor chip packaging technologies. While front-end silicon technology has followed Moore's Law to make semiconductor components smaller and smaller, back-end infrastructure has lagged behind similar advances. [0003] Fan-out wafer-level packaging (FOWLP) is an embedded package processed at the wafer level, and it is also one of the main advanced packages with a large number of I / Os and good integration flexibility. Fan-out wafer-level packaging technology uses wafer-level thin-film technology to connect chips and extern...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/31H01L23/498H01L21/56H01L21/60
CPCH01L21/568H01L24/19H01L24/96H01L24/97H01L2224/04105H01L2224/12105H01L2224/82103H01L2924/18162H01L21/56H01L23/31H01L23/498
Inventor 林正忠汤红
Owner SJ SEMICON JIANGYIN CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com