Method for forming semiconductor device

Abstract

A method for forming a semiconductor device, comprising: providing a substrate, the substrate having a first region, a sacrificial layer on the surface of the substrate, and a semiconductor layer on the surface of the sacrificial layer; the semiconductor layer and the sacrificial layer in the first region At least three adjacent first trenches are formed in the layer, the first trenches expose the surface of the substrate, the semiconductor layer between the first trenches forms at least two parallel nanowires, and the adjacent nanowires are formed. The distance between the nanowires is the same, and the nanowires include device nanowires and dummy nanowires; the sacrificial layer at the bottom of the nanowires is removed, so that the nanowires are suspended above the substrate; after removing the sacrificial layer in the first area, the first time The annealing process makes the cross section of the nanowires round; after the first annealing process, the dummy nanowires are removed. The formed semiconductor device has improved morphology and improved performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor device. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration. Transistors, as the most basic semiconductor devices, are currently being widely used. Therefore, as the component density and integration of semiconductor devices increase, the gate size of transistors is also getting shorter and shorter. However, the shortening of the gate size of the transistor will cause the short-channel effect of the transistor, thereby generating leakage current, and ultimately affecting the electrical performance of the semiconductor device. [0003] In order to overcome the short channel effect of the transistor and suppress the leakage current, the prior art proposes a fully surrounded gate nanowire ...

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Problems solved by technology

[0006] However, the nanowires formed by the prior art have poor morphology, resulting in poor formation performance of the formed gate-all-around nanowire transistors.

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