IO circuit used for enhancing ESD performance

Abstract

The invention discloses an IO circuit used for enhancing ESD performance. The IO circuit comprises a detection circuit, a preceding-stage driving circuit, an ESD protection tube and an IO driving tube. The detection circuit is formed through connecting a resistor and a capacitor in series. The preceding-stage driving circuit is formed by a MOS with a moderate size. The ESD protection tube and the IO driving tube are reused and are formed by a large-size NMOS and a large-size PMOS. The resistor R and the capacitor C form the detection circuit. The detection circuit can detect an ESD event and is served as input of preceding stage driving. The preceding-stage driving circuit controls switches of the large-size NMOS and the large-size PMOS. The large-size NMOS and the large-size PMOS timely and effectively release static electricity in the ESD event and are taken as driving tubes of the IO circuit during normal working. Compared to a conventional method, by using the IO circuit of the invention, in order to reach a same ESD level, needed NMOS and PMOS areas are greatly reduced and a circuit area is effectively decreased through reusing of an ESD protection device and the driving tube.

Description

technical field [0001] The invention belongs to the technical field of chips, in particular to an IO circuit with ESD performance. Background technique [0002] The IO circuit is a bridge connecting the integrated circuit and the external circuit. When ESD (Electro-Static Discharge) occurs, the IO circuit protects itself and the internal circuit. If the IO circuit cannot effectively discharge the static electricity in time, it will cause the integrated circuit to fail. Improve the ESD performance of the IO circuit, so that the integrated circuit needs to have a certain level of ESD to avoid failure in production, transportation, application and other links. [0003] To discharge static electricity, it is necessary to provide a low-resistance path for static electricity. The conventional method is to use the source-drain breakdown of large-size NMOS or PMOS to trigger the parasitic BJT to turn on and enter the snapback, and to release the static electricity in time and effe...

AI Technical Summary

Problems solved by technology

However, although this circuit protects the ESD circuit itself through the primary protection circuit and the secondary protection circuit, due to the breakdown of the device involved, the trigger voltage is very high, and the ESD level that can be achieved is limited.

There is a risk of breakdown and poor reliability

When the ESD requirements are high, the area occupied by the ESD protection device is relatively large; further, when the driving capability is required, additional driving devices are required, which greatly increases the circuit area

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