Distributed algorithm applied to FIR filters

Abstract

The invention relates to the field of digital filters, and specifically relates to a distributed algorithm applied to FIR filters. The distributed algorithm comprises the following steps: an analog input signal X[n] is converted by an analog-to-digital conversion module into a B-bit digital signal; the B-bit digital signal is processed in a shift register as input data, and the processing result is sent to a serial-parallel module; the serial-parallel module transmits the input data to a binary bit weight multiplication module, rearranges the input data according to the binary bit weight, and outputs the input data to a parallel-serial module; the parallel-serial module divides the input data into B groups of bit stream data according to 2<0>, 2<1>,...,2<B-1>; the B groups of bit stream data respectively enter n groups of look-up table modules for table look-up and addition operation, and B groups of output data are worked out according to a two-dimension DA algorithm formula (shown in the description), thus obtaining an output signal Y[n] after filtering. The use of memory resources and logical unit resources is reduced, and FPGA resources are fully utilized.

Description

technical field [0001] The invention relates to the field of digital filters (namely FIR filters), in particular to a distributed algorithm applied to FIR filters. Background technique [0002] Existing FIR filters are mainly used in touch control circuits. For example, FIR filters are used in the touch screen control circuit CS9603 currently on the market. At present, the existing FIR filter adopts a direct accumulation structure and directly uses a multiplier and an adder to realize a convolution operation, so as to achieve the purpose of filtering. [0003] as attached figure 1 As shown, it is a block diagram of the existing FIR filter applied to the peripheral circuit, in which the filter configuration (fir_mcu_if) module is to receive the address, data, filter coefficient and enable information sent by the main control chip to control the action of the filter, Standard timing is used. The data processing (Data_process) module judges the frame scan, line scan, whether...

AI Technical Summary

Problems solved by technology

Because the multiplier occupies too much resources, those skilled in the art have successively proposed the application of the shift-add unit to replace the multiplier in the direct type. However, the resource utilization rate of this structure for the field programmable gate array (FPGA) is too low.

In order to solve the problem that the multiplier occupies too much resources and the utilization rate of FPGA resources is too low, there is a kind of processing method based on distributed algorithm. This two-dimensional algorithm uses shift and addition method to reduce memory usage and increase Delay module to avoid confusion caused by timing design to ensure the correctness of output results

Also due to the addition of the delay module, too many shifters are used, which offsets the memory resources saved by the shift and add module, and does not actually save memory resources and logic elements (LE)

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