LDMOS transistor and forming method thereof

Abstract

Disclosed are an LDMOS transistor and a forming method thereof. The LDMOS transistor comprises a transistor body region and a shifting region which are located on a semiconductor substrate, a gate region, a source region located in the transistor body region, a leakage region located in the shifting region, a first isolation structure and a control electrode; a clearance is formed between the transistor body region and the shifting region; the gate region spans above the transistor body region and the shifting region; the source region and the leakage region are located on two sides of the gate region; the first isolation structure is located in the shifting region and between the gate region and the leakage region; the control electrode is located on the first isolation structure, and the bottom of the control electrode is located in the first isolation structure. The LDMOS transistor has the advantages that the size increase is avoided, the breakdown voltage is increased, and the conduction resistance is decreased.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an LDMOS transistor and a forming method thereof. Background technique [0002] Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistors are mainly used in power integrated circuits, such as RF power amplifiers for mobile phone base stations, and can also be used in high frequency (HF), very high frequency (VHF) and Ultra-high frequency (UHF) broadcast transmitters and microwave radar and navigation systems, etc. LDMOS technology brings higher power peak-to-average ratio, higher gain and linearity to the new generation of base station amplifiers, and at the same time brings higher data transmission rates to multimedia services. [0003] For an LDMOS transistor used as a power integrated circuit, its on-resistance (Rdson) and breakdown voltage (Breakdown Voltage, BV) are two important indicators to measure its device performance. For LDMOS, it is usually expect...

AI Technical Summary

Problems solved by technology

[0005] However, increasing the lateral distance FX of the isolation structure 31 brings adverse effects in three aspects at the same time: 1. The on-resistance increases; 2. The electric field at the edge of the gate 42 and the isolation structure 31 increases, which increases the risk of breakdown; 3. No Suitable for today's device size reduction trend

[0006] For this reason, a new LDMOS transistor and its formation method are needed to prevent the problems of increased on-resistance, enhanced fringe electric field and increased device size when the breakdown voltage is increased

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