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Instruction set transition system and method

A conversion method and technology of a conversion system, which are applied in the direction of operation instruction conversion, address formation of the next instruction, memory system, etc., and can solve the problems of capacity waste and low tracking cache performance, etc.

Inactive Publication Date: 2015-06-03
SHANGHAI XINHAO MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, a large number of instructions with duplicate addresses but located on different paths will be stored in the trace cache, resulting in a large waste of capacity, resulting in low performance of the trace cache

Method used

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  • Instruction set transition system and method
  • Instruction set transition system and method
  • Instruction set transition system and method

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Embodiment Construction

[0068] The high-performance caching system and method proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. Advantages and features of the present invention will be apparent from the following description and claims. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[0069] It should be noted that, in order to clearly illustrate the content of the present invention, the present invention specifically cites multiple embodiments to further explain different implementation modes of the present invention, wherein the multiple embodiments are enumerated rather than exhaustive. In addition, for the sake of brevity of description, the content mentioned in the previous embodiment is often omitted in the latter embodiment, ther...

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Abstract

Provided are an instruction set conversion system and method, capable of converting an external instruction into an internal instruction for a processor core (1201) to execute, and conveniently expanding, via configuration, an instruction set supported by a processor system. Also provided is a method for real-time conversion between an internal instruction address and an external instruction address, enabling the processor core (1201) to directly read the internal instructions in an upper level cache, thus reducing the depth of a pipeline.

Description

technical field [0001] The invention relates to the fields of computer, communication and integrated circuit. Background technique [0002] At present, if programs belonging to different instruction sets need to be executed on a certain processor core, the most common method is to use a software virtual machine (or virtualization layer). The function of the virtual machine is to translate or interpret the program composed of the instruction set (external instruction set) not supported by the processor core, and generate instructions corresponding to the instruction set (internal instruction set) supported by the processor core itself for execution. Generally speaking, the method of interpretation is to use the virtual machine to sequentially take out the various fields in the external instructions, including opcodes and operands, through software methods in real time during the running process, and then use the stack structure implemented in the memory. The code performs th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/32G06F12/10G06F12/0875
CPCG06F9/3017G06F9/3004G06F9/3802G06F12/0875G06F2212/452
Inventor 林正浩
Owner SHANGHAI XINHAO MICROELECTRONICS
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