Array substrate, manufacturing method thereof, and display device

A technology for array substrates and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., and can solve problems such as crystallization, increased complexity of the array substrate manufacturing process, and inability to etch, Achieve the effect of simplifying the manufacturing steps and preventing electrochemical corrosion

Active Publication Date: 2018-08-07
BOE TECH GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since the deposition temperature of the passivation layer is about 300°C to 350°C, and the annealing temperature of ITO is about 250°C to 270°C, if the ITO is etched after the passivation layer is deposited, the ITO will crystallize and cannot be etched. Therefore, it is necessary to etch the ITO after depositing the ITO, then deposit the passivation layer, and then etch the passivation layer, which leads to an additional patterning process and increases the complexity of the array substrate manufacturing process.

Method used

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  • Array substrate, manufacturing method thereof, and display device
  • Array substrate, manufacturing method thereof, and display device
  • Array substrate, manufacturing method thereof, and display device

Examples

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Embodiment 1

[0033] This embodiment provides a method for fabricating an array substrate, such as Figure 1 to Figure 8 As shown, the method includes the following steps:

[0034] Step S1: forming a plurality of first via holes 5 and a plurality of second via holes 6 on the substrate 1 on which the thin film transistors have been manufactured.

[0035] Step S2: covering the transparent conductive layer 7 on the substrate 1 after the first via hole 5 and the second via hole 6 are formed.

[0036] Step S3 : covering the transparent conductive layer 7 with a protective material layer 8 , the film forming temperature of the protective material layer is lower than the annealing temperature of the transparent conductive layer 7 .

[0037] Step S4: Forming the first electrode 12 covering the first via hole 5 and its surroundings, the second electrode 13 covering the second via hole 6 and its surroundings, and the first protective layer 10 covering the first electrode 12 by one patterning process ...

Embodiment 2

[0063] This embodiment provides an array substrate, including: a substrate and a thin film transistor on the substrate, such as Figure 8 As shown, the array substrate also includes: a plurality of first via holes and a plurality of second via holes arranged on the substrate 1; a first electrode 12 covering the first via holes and their surroundings; a second electrode covering the first electrode 12 A protective layer 10; covering the second via hole and the second electrode 13 around it. Wherein, the film forming temperature of the first protection layer 10 is lower than the annealing temperature of the first electrode 12 and the second electrode 13, and the first protection layer 10, the first electrode 12 and the second electrode 13 are formed in the same patterning process.

[0064] Since the first electrode 12 is covered with the first protective layer 10, the first protective layer 10 can protect the first electrode 12, effectively preventing the electrochemical corrosi...

Embodiment 3

[0069] This embodiment provides a display device, including the array substrate described in the second embodiment. Since the array substrate described in Embodiment 2 can protect the first electrode 12 by using the first protection layer 10 on the premise of saving the number of patterning processes and simplifying the manufacturing steps, so as to prevent the first electrode 12 from deteriorating, the The provided display device also has the advantage of preventing the deterioration of the first electrode 12 under the premise of saving the number of patterning processes and simplifying the manufacturing steps, and has higher reliability and display quality.

[0070] It should be noted that the display device provided in this embodiment can be a liquid crystal panel, electronic paper, OLED (Organic Light-Emitting Diode, organic light-emitting diode) panel, mobile phone, tablet computer, television, monitor, notebook computer, digital photo frame , navigator and any other prod...

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PUM

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Abstract

The invention provides an array substrate, a manufacturing method thereof, and a display device, which relate to the field of display technology and are used to solve the problem of increased patterning times caused by the production of a passivation layer protecting ITO on ITO. The manufacturing method of the array substrate includes: forming a plurality of first via holes and a plurality of second via holes on the substrate on which the thin film transistors are fabricated; and covering a transparent conductive layer on the substrate after the first via holes and the second via holes are formed ; Cover the transparent conductive layer with a protective material layer, and the film forming temperature of the protective material layer is lower than the annealing temperature of the transparent conductive layer; Use a patterning process to form a first electrode covering the first via hole and its surroundings, and covering the second via hole and a second electrode around it, and a first protective layer covering the first electrode. The array substrate, the manufacturing method thereof, and the display device provided by the present invention are used for displaying images.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display device. Background technique [0002] In the GOA (Gate Driver on Array, array substrate row drive) technology, the GOA unit is integrated on the array substrate of the display device, which includes a plurality of thin film transistors, and each GOA unit is connected to each gate line on the array substrate, thereby Realize the scan driving of the gate lines. [0003] The manufacturing process of the GOA array substrate is roughly as follows: firstly, thin film transistors are fabricated on the base substrate, and these thin film transistors include thin film transistor arrays located in the display area and thin film transistors located in the frame area to form GOA units, and then fabricated in the frame area The first via hole and the second via hole, and then deposit ITO (Indium Tin Oxide, indium tin ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/84H01L27/12H01L23/50
Inventor 陈曦高英强郭总杰刘正张治超张小祥刘明悬
Owner BOE TECH GRP CO LTD
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