A method for modeling a field effect transistor and a circuit simulation method

Abstract

The invention relates to a method for modeling a field effect transistor and a circuit simulation method. The method for modeling the field effect transistor includes calling the gate voltage and the corresponding drain current recorded by the selected field effect transistor to obtain the variation of the drain current of the field effect transistor with the gate voltage relationship; based on the relationship between the drain current of the field effect transistor and the gate voltage change, the relationship between the first equivalent drain current of the transistor structure and the gate voltage change and the shallow trench isolation structure The relationship between the second equivalent drain current and the variation of the gate voltage; according to the relationship between the first equivalent drain current of the transistor structure and the variation of the gate voltage and the second relationship of the shallow trench isolation structure The relationship between the equivalent drain current and the variation of the gate voltage establishes a field effect transistor model. The invention can establish an accurate field effect transistor model to improve the accuracy of circuit simulation.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a method for modeling a field effect transistor and a circuit simulation method. Background technique [0002] Shallow trench isolation (STI) technology is used to realize isolation between field effect transistors (MOSFETs). The formation principle of the shallow trench isolation structure is to etch a groove on the surface of the silicon substrate corresponding to the shallow trench, and silicon dioxide (SiO 2 ) into the groove. [0003] Shallow trench isolation technology is a substitute for partial isolation silicon oxide isolation technology, and is the mainstream isolation technology for deep submicron processes. The trench of the shallow trench isolation structure has relatively steep side walls, so it has a small area, which can improve the integration degree of the field effect transistor. And because the CMP process is used in its manufacturing process, it ha...

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Problems solved by technology

[0006] However, the field effect transistor model in the prior art simulation system based on BSIM4 etc. ignores the impact of the shallow trench isolation structure on the transistor structure: when the size of the field effect transistor is relatively large, the shallow trench isolation structure has a large impact on the field effect transistor. The impact of parameters and performance can be ignored; but with the continuous development of the integrated circuit industry, the size of the field effect transistor is continuously reduced. The field effect transistor model does not take this result into account and cannot accurately describe the characteristics of real field effect transistors

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