Mask read only memory and manufacturing method thereof

Abstract

The invention discloses a mask read only memory. A conducting channel between a source and a drain of a device can be cut off by arranging a shallow trench field oxide at a region covered by a source region, a drain region or a gate structure of an NMOS (N-channel metal oxide semiconductor) storage unit so as to realize encoding setting 1; the source region and the drain region which are not provided with the shallow trench field oxide are also kept in heavily doped structures; the region covered by the gate structure is also kept into a P well structure; thus the drain region and the source region can be shared between the drain region and each adjacent NMOS storage unit connected with a same bit line, and the drain region is not required to be arranged independently. The invention also discloses a manufacturing method of the mask read only memory. The area of the device can be reduced, the integration of the device can be improved, the process cost is reduced, a new photo-mask layer is not required to be additionally arranged, and the electric leakage can also be reduced.

Description

technical field [0001] The invention relates to the field of manufacturing semiconductor integrated circuits, in particular to a mask read-only memory; the invention also relates to a manufacturing method of the mask read-only memory. Background technique [0002] Programmable read-only memory (Read-Only Memory, ROM) includes mask type read-only memory (MASK ROM). The content of MASK ROM can be customized by the user, and then realized by the mask process in the integrated circuit manufacturing process to meet user needs ROM programming. [0003] The encoding method commonly used in the existing first Mask ROM is: to encode 0 and 1 on the NMOS storage unit device by setting the presence or absence of the through hole (Via) at the drain terminal. The MASK ROM formed by this encoding is called ViaROM for short. Such as figure 1 As shown, it is the cross-sectional view of the NMOS storage unit of the existing first mask type read-only memory, Via ROM; figure 2 Shown is the ...

AI Technical Summary

Problems solved by technology

[0007] Depend on figure 1 and figure 2 It can be seen that since the existing first mask type ROM needs to set the contact hole 111 above the drain region to program the NMOS memory cell, the storage information of each NMOS memory cell is completely determined by the drain region, so it cannot be realized. Two adjacent NMOS memory cells share the same drain region, so the prior art can only share the source region between two adjacent NMOS memory cells, and cannot realize the drain region process, so in the prior art, one has Only two NMOS memory cells can be set in the source region 103, and the shallow trench field oxygen must be used to isolate each active region, so the excessive setting of the drain region and the excessive setting of the shallow trench field oxygen are greatly reduced. Increase the area of ​​the device, reduce the integration of the device, and increase the process cost

[0008] The existing second mask ROM usually adopts channel ion implantation encoding, that is, the device is encoded by setting different turn-on voltages for the device by ion implantation in the channel region of the device, that is, the NMOS memory unit device. The ROM array encoded by ion implantation has a relatively small array area due to the common source or drain area, but additional mask levels are added

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