Integrated nonpolar gan nanowire high electron mobility transistor and its preparation method

A high electron mobility, nanowire technology, applied in the fields of nanotechnology, nanotechnology, semiconductor/solid-state device manufacturing, etc., can solve the problems of uneven distribution of nanowires, low yield, disorder, etc., to solve the problem of uncontrollable The effect of simplification of process steps and optimization of process methods

Active Publication Date: 2017-09-26
JIANGSU INST OF ADVANCED SEMICON CO LTD
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  • Description
  • Claims
  • Application Information

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Problems solved by technology

This preparation technology separates the nanowire epitaxial growth from the device preparation, which increases the complexity of the process
Nanowires are transferred by coating with nanowire suspension, which makes the arrangement of nanowires uneven and disordered, and the yield is low, which cannot achieve the purpose of integrated controllable mass production

Method used

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  • Integrated nonpolar gan nanowire high electron mobility transistor and its preparation method
  • Integrated nonpolar gan nanowire high electron mobility transistor and its preparation method
  • Integrated nonpolar gan nanowire high electron mobility transistor and its preparation method

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preparation example Construction

[0041] refer to image 3 , an integrated non-polar GaN nanowire high electron mobility transistor preparation method, comprising the following steps:

[0042] A. A patterned semiconductor substrate 1 structure is provided, and the semiconductor substrate 1 structure includes a substrate 1 and an insulating dielectric layer 2 positioned on the substrate 1;

[0043] B. Etching and forming a plurality of grooves 3 on the insulating dielectric layer 2;

[0044] C. Epitaxial growth on the sidewalls 31 of each groove 3 to form heterojunction nanowires 4;

[0045] D. Forming a source electrode 5 and a drain electrode 6 on the insulating medium layer 2 located on both sides of the heterojunction nanowire 4, and connecting the source electrode 5 and the drain electrode 6 to each heterojunction nanowire 4;

[0046] E. A gate 7 structure is formed between the source 5 and the drain 6 , the gate 7 structure includes the gate 7 and the gate dielectric layer 8 between the gate 7 and the h...

Embodiment 1

[0054] Embodiment 1, in conjunction with reference Figure 1 ~ Figure 3 Step A is performed to provide a structure of a semiconductor substrate 1 , the structure of the semiconductor substrate 1 includes a substrate 1 and an insulating dielectric layer 2 on the substrate 1 . The material of the substrate 1 is single crystal silicon; the material of the insulating dielectric layer 2 on the substrate 1 is a silicon dioxide layer or silicon nitride, but it is not limited to these two dielectric layers, which can be well known by those skilled in the art. other media layers. The semiconductor substrate 1 is patterned to form an array of rectangular grooves 3 . Wherein forming the rectangular groove 3 of the array comprises: coating photoresist layer on the surface of the silicon dioxide layer; defining the rectangular groove 3 pattern of the array on the photoresist layer; wet etching the silicon dioxide layer; removing the photoresist; wet etching the bottom surface of the groo...

Embodiment 2

[0058] Embodiment 2, in conjunction with reference Figure 1 ~ Figure 3 , to provide a structure of a semiconductor substrate 1 , the structure of the semiconductor substrate 1 includes a substrate 1 and an insulating dielectric layer 2 on the substrate 1 . The material of the substrate 1 is single crystal silicon, and the material of the insulating dielectric layer 2 on the substrate 1 is a silicon dioxide layer or silicon nitride, but it is not limited to these two dielectric layers, which can be known to those skilled in the art. other media layers. The semiconductor substrate 1 is patterned to form an array of rectangular grooves 3 . Wherein forming the rectangular groove 3 of the array comprises: coating photoresist layer on the surface of the silicon dioxide layer; defining the rectangular groove 3 pattern of the array on the photoresist layer; wet etching the silicon dioxide layer; removing the photoresist; wet etching the bottom surface of the groove 3 and the sidewa...

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Abstract

The invention discloses an integrated nonpolar GaN nanowire transistor high in electron mobility and a preparation method thereof. The transistor comprises a substrate and an insulating dielectric layer located on the substrate, a plurality of grooves at intervals are etched in the insulating dielectric layer, heterojunction nanowires are respectively grown in the grooves, a source electrode and a drain electrode are formed on the insulating dielectric layer and are respectively located at two ends of the heterojunction nanowires and respectively connected with each heterojunction nanowire, a gate electrode is formed between the source electrode and the drain electrode, and a gate dielectric layer is arranged between the gate electrode and the heterojunction nanowires. According to the transistor, epitaxial growth and device preparation are united organically, process steps are greatly simplified, and the method is simplified. The transistor solves the problem of uncontrollability and disorder caused by the solution dilution and coating for current nanowire transistors, the nanowire transistor preparation success rate is effectively improved. The nanowire transistor can be widely applied to the field of semiconductors.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to an integrated nonpolar GaN nanowire high electron mobility transistor and a preparation method thereof. Background technique [0002] Microelectronic integrated circuits and technologies are key factors and core technologies for the rapid development of modern electronic information technology. With the development of microelectronics integration technology, the integration degree of microelectronic devices mainly made of Si material is getting higher and higher, and the feature size of the device is required to be smaller and smaller. When the minimum feature size is 10nm, the physical limit of microelectronic devices is reached, and Moore's law no longer holds true. This is because nano-semiconductor devices of this size differ from microelectronic devices in their working mechanism, materials and process technology. [0003] Nanoelectronic devices are called th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/778H01L21/335B82Y10/00
CPCH01L29/0669H01L29/66462H01L29/7786
Inventor 李述体李凯于磊王幸福
Owner JIANGSU INST OF ADVANCED SEMICON CO LTD
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