A Reconfigurable Architecture Platform Design Method for Image Processing

Abstract

The invention discloses an image processing-oriented reconfigurable architecture platform design method. The design method first analyzes and summarizes the various operation types of commonly used complex algorithms. Secondly, the image algorithm processing flow is divided into software and hardware under the reconfigurable architecture. Then, the reconfigurable unit design and implementation of multi-type image algorithm operation types are carried out, and on this basis, the scheme design and technical implementation of the general complex algorithm global interconnection architecture are carried out. Finally, based on this architecture, the design and implementation of a general convolution operation IP core is carried out.

Description

technical field [0001] The invention belongs to the technical field of reconfigurable design, in particular to an image processing-oriented reconfigurable architecture platform design method. Background technique [0002] At present, image processing for applications in various fields is becoming more and more complex, and various image processing algorithms (such as image preprocessing, image detection, tracking, etc.) have a huge amount of computation, and at the same time have extremely high real-time requirements. The co-processing architecture based on DSP+FPGA is a commonly used method at present. On the basis of realizing the software and hardware division of related algorithms, the software flexibility of DSP and the real-time performance of FPGA hardware are fully utilized to realize the cooperative work and reliable operation of system software and hardware. [0003] The complex algorithm processing based on the FPGA chip consumes huge hardware resources, which le...

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Problems solved by technology

[0003] The hardware resources consumed by complex algorithm processing based on FPGA chips are very huge, which leads to the selection of foreign high-end FPGA chips in the design and selection. These chips cannot find localized alternative FPGA chips in the short term.

As the integration level of system design becomes higher and higher, traditional image algorithm processing solutions cannot solve the contradiction between algorithm performance improvement and resource consumption reduction. Gain the efficiency and performance of an ASIC

[0004] The reconfigurable processor developed in recent years has been extensively researched. The reconfigurable architecture absorbs the configurable characteristics of DSP and FPGA in terms of flexibility, and adopts a structure with a larger granularity to obtain performance improvement while reducing the The complexity of configuration improves resource utilization. Although the generality is reduced, it can still meet the needs of specific fields and obtain the efficiency close to ASIC.

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