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Packaging substrate, semiconductor package and fabrication methods thereof

A technology for packaging substrates and semiconductors, which is applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, and semiconductor/solid-state device components, etc., can solve problems such as increased production costs, product scrap, scratches on the second surface 11b, etc. cost, the effect of avoiding chipping

Active Publication Date: 2014-08-27
SILICONWARE PRECISION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] However, in the existing semiconductor package 1, before the semiconductor component 15 is installed, the second surface 11b of the first encapsulant 11 is exposed, so the first encapsulant 11 is easily damaged by handling or external impact. The second surface 11b is scratched, or the first encapsulant 11 is cracked, causing the product to be scrapped
[0014] In addition, the second electrical connection pad 122 is exposed before the packaging process, so it needs to be protected by Organic Solderability Preservative (OSP) to prevent the second electrical connection pad 122 from being oxidized. cost of production

Method used

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  • Packaging substrate, semiconductor package and fabrication methods thereof
  • Packaging substrate, semiconductor package and fabrication methods thereof
  • Packaging substrate, semiconductor package and fabrication methods thereof

Examples

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Embodiment Construction

[0068] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0069] It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not intended to limit the implementation of the present invention. Limiting conditions, so there is no technical substantive meaning, any modification of structure, change of proportional relationship or adjustment of size, without affecting the effect and purpose of the present invention, should still fall within the scope of the present invention. The disclosed technical content must be within the scope covered. At the same time, terms such as "above", "first", "second" and...

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Abstract

A packaging substrate is disclosed, which includes: an encapsulant having opposite first and second surfaces; a plurality of conductive elements embedded in the encapsulant, wherein each of the conductive elements has a first conductive pad exposed from the first surface of the encapsulant and a second conductive pad exposed from the second surface of the encapsulant; and a protection layer formed on the second surface of the encapsulant and the second conductive pads so as to protect the second surface of the encapsulant from being scratched.

Description

technical field [0001] The invention relates to a semiconductor package, in particular to a semiconductor package with improved yield rate and a manufacturing method thereof. Background technique [0002] With the evolution of semiconductor packaging technology, different packaging types have been developed for semiconductor packages. In the prior art, the semiconductor package mainly forms a multi-layer circuit structure on a core layer to make a packaging substrate, and then installs The chip is placed on the packaging substrate, and the chip is electrically connected to the multi-layer circuit structure, and finally packaged with packaging glue. However, since the core layer of the package substrate formed in this way occupies a certain thickness, it is limited to reduce the thickness of the package. Therefore, the industry has developed a package substrate without a core layer, which omits the use of the core layer to reduce the height of the package, and this package c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/31H01L21/56
CPCH01L24/97H01L2924/15311H01L23/3128H01L24/96H01L2224/97H01L2224/48227H01L2224/32225H01L21/4846H01L21/56H01L23/49816H01L23/49827H01L23/49861H01L24/29H01L24/48H01L2224/16225H01L2224/2919H01L2224/48091H01L2224/73265H01L2224/85444H01L2224/85455H01L2224/85464H01L2924/00014H01L2924/181H05K3/007H05K3/4007H05K2203/0152H05K2203/0726Y10T29/49155H01L2224/85H01L2224/83H01L2224/45099H01L2924/00012H01L2924/00
Inventor 林邦群蔡岳颖陈泳良
Owner SILICONWARE PRECISION IND CO LTD
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