Salient point structure for preventing salient point lateral etching and forming method

Abstract

The invention relates to a semiconductor structure and manufacturing method thereof, in particular to a salient point structure for preventing salient point lateral etching and a forming method and belongs to the technical field of semiconductor manufacturing. In the technical scheme, the salient point structure for preventing the salient point lateral etching comprises a substrate and an insulating layer located on the substrate. A metal bonding pad is arranged on the insulating layer, an outer ring of the metal bonding pad is provided with a dielectric layer, the dielectric layer covers the insulating layer and the edge of the outer ring of the metal bonding pad. A copper column is arranged right above the metal bonding pad, the bottom end of the copper column sequentially passes through a seed layer and an adhesion layer to be in contact with and electrically connected with the metal bonding pad and is supported on the dielectric layer through the seed layer and the adhesion layer, and welding flux salient points are arranged at the top end of the copper column. The salient point structure for preventing the salient point lateral etching adopts a method for firstly imaging the adhesion layer, the problem that the lateral etching is easily caused during adhesion layer removal after electroplating is solved, and the reliability and yield of machined and manufactured salient points are improved.

Description

technical field [0001] The invention relates to a semiconductor structure and a preparation method thereof, in particular to a bump structure and a molding method for preventing lateral etching of bumps, and belongs to the technical field of semiconductor manufacturing. Background technique [0002] Traditionally, the electrical connection between the IC chip and the outside is achieved by bonding the I / O on the chip to the package carrier through metal wires through the package pins. With the reduction of IC chip feature size and the expansion of integration scale, the pitch of I / O is decreasing and the number is increasing. When the I / O pitch is reduced below 70 μm, the wire bonding technology is no longer applicable, and new technical approaches must be sought. [0003] Wafer-level packaging technology uses thin film redistribution technology, so that I / O can be distributed on the entire surface of the IC, rather than limited to the peripheral area of ​​​​the narrow IC c...

AI Technical Summary

Problems solved by technology

Due to the problem of undercutting, the selection of etching solution and the control of etching process will be limited when etching the seed layer

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