Addressable test chip and test method thereof

Abstract

The invention discloses an addressable test chip and a test method thereof. The test chip consists of an addressable circuit, a plurality of test frameworks and a plurality of test structure groups which are placed among the test frameworks, wherein the addressable circuit consists of a peripheral address decoding circuit and a plurality of switch circuits. The peripheral address decoding circuit consists of a row address decoding circuit, a column address decoding circuit and a pin selection decoding circuit. All the input ends of the row address decoding circuit, the column address decoding circuit and the pin selection decoding circuit are connected with a PAD set, and the output ends are connected with the switch circuits; the switch circuits are also connected to a PAD signal location by the plurality of signal lines; the switch circuits are connected with the test structure groups by the test frameworks. During test, the test frameworks are selected by row address signals and column address signals, signal selection pins are selected by pin selection signals, and test structures are tested by test signals. By means of the pin selection circuit, the addressable test chip and the test method can test the test structure group with a plurality of pins.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to an addressable test chip for testing whether there is a defect in a semiconductor production process and a testing method thereof. Background technique [0002] Traditional semiconductor manufacturing uses short-range test chips to test the defect rate and yield of the production process. According to the location in the wafer, it can be divided into two categories: independent test chips and test chips placed in dicing grooves. The independent test chip has a large area and needs to occupy the position of a chip, which is equivalent to the semiconductor manufacturer needing to pay the manufacturing cost of this part of the area mask. The dicing slot is the space reserved for cutting chips on the wafer. The test chip is placed in the dicing slot without occupying the position of the chip. This saves semiconductor manufacturers from having to bear expensive mas...

AI Technical Summary

Problems solved by technology

[0008] The present invention mainly solves the technical problems existing in the prior art that the area utilization rate is small and cannot detect typical devices with multiple layers and multiple pins, and provides a test addressable device with pin selection capability and high area utilization rate. Method for testing chip and test circuit for typical device in semiconductor production process

Images