Construction Method of On-Chip Network Topology Structure Based on Bufferless Router Architecture

Abstract

The invention relates to a construction method for a network-on-chip topological structure based on a no-buffer router framework. On the basis of a traditional centralized mesh topological structure, each router and adjacent routers in horizontal and longitudinal directions are connected together through bidirectional data channels; all routers in each line and each row are connected together through bidirectional buses to form a redundant centralized mesh-bus structure. For the multiple routers in a single line or row, not only can data be transmitted step by step through mesh lines but also the data can directly arrive at the destination through the buses. Under the condition that conflicts occur due to path selection during the transmission process of data packets, one of the data packets can be transmitted through the buses, and the other data packet can be transmitted through the mesh lines; the two data packets do not deviate from the optimal line, and therefore, the probability that the data packets deflect to other lines or rows is reduced, the influence on the transmission of other data packets is reduced, and the average delay and the energy consumption of the whole network on a chip are reduced.

Description

technical field [0001] The invention belongs to the field of computer architecture, and in particular relates to a method for constructing an on-chip network topology based on a bufferless router architecture. Background technique [0002] As single-chip multiprocessor architectures integrate more and more cores, the quality of communication between components becomes critical in order for the various components on the chip to work together. As the communication medium of on-chip components, the network-on-chip has low latency, low energy consumption, and high scalability, which are the core of the network-on-chip research. [0003] The number of routers and path length through which data packets communicate in the topology directly affects the average delay and overall energy consumption of the network on chip. The greater the number of routers through and the greater the path length, the higher the latency and the higher the energy consumption; and vice versa. [0004] T...

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Problems solved by technology

[0006] In order to overcome the disadvantages of the existing topological structure such as high average delay and high energy consumption when using the bufferless router architecture, the present invention proposes a network based on the centralized mesh structure (Concentration Mesh, referred to as CMesh). Construction method of centralized mesh and bus combined network topology (CMesh-Bus) based on buffer router architecture

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