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Three-dimensional laminated semiconductor structure and manufacturing method thereof

A manufacturing method and semiconductor technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve problems such as lowering resistance, failure to operate smoothly, and influence on reading speed of three-dimensional stacked flash memory

Active Publication Date: 2014-04-16
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the polysilicon layer 133 of the three-dimensional stacked structure in the fan-out region 13 still needs to undergo an ion implantation process to reduce its resistance value.
If the resistance value of the polysilicon layer 133 is not lowered, the reading speed of the three-dimensional stacked flash memory will be seriously affected, resulting in delays or even failure to operate smoothly.
The current existing method is to implant the polysilicon layer 133 layer by layer in the fan-out region 13, which is very time-consuming and cost-intensive.

Method used

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  • Three-dimensional laminated semiconductor structure and manufacturing method thereof
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  • Three-dimensional laminated semiconductor structure and manufacturing method thereof

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Embodiment Construction

[0035] In embodiments of this disclosure, three-dimensional stacked semiconductor structures and related fabrication methods are presented. The three-dimensional stacked semiconductor structure proposed in the embodiment can reduce the resistance value of the structure without the time-consuming and expensive multi-channel ion implantation process, especially the resistance value of the bit line through which the operating current passes, and greatly accelerate the three-dimensional fast application. Flash memory read speed. Therefore, the embodiment not only has low manufacturing cost through fast process steps, but also enables the application memory to have stable and faster operation performance as a whole.

[0036] Related embodiments are provided below to describe in detail the three-dimensional stacked semiconductor structure proposed by the present invention and the related manufacturing method. However, the descriptions in the embodiments, such as detailed structures...

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Abstract

The invention discloses a three-dimensional laminated semiconductor structure and a manufacturing method of the three-dimensional laminated semiconductor structure. The three-dimensional laminated semiconductor structure comprises a plurality of oxide layer, a plurality of conducting layers, at least one contact hole, an insulating layer and conducting object material, wherein the multiple oxide layers and the multiple conducting layers are laminated in a staggered mode; the at least one contact hole is arranged perpendicular to the multiple oxide layers and the multiple conducting layers and extends to one of the conducting layers; the insulating layer is formed on the two sides of the contact hole; the conducting object material is filled into the contact hole and connected with the corresponding conducting layer; the conducting layer corresponding to the contact hole comprises metal silicide, and the metal silicide can be formed on the edge or all of the corresponding conducting layer. A conducting material can be formed by the corresponding conducting layer partially or totally except the metal silicide so as to be connected with the conducting object material. The conductivity of the conducting layer corresponding to the contact hole is higher than that of the other conducting layers. The three-dimensional laminated semiconductor structure can be applied to structures such as a fan-out area of a three-dimensional flash memory.

Description

technical field [0001] Embodiments of the present invention relate to a three-dimensional stacked semiconductor structure and a manufacturing method thereof, and particularly relate to a three-dimensional stacked semiconductor structure of a fan-out region of a three-dimensional flash memory and a manufacturing method thereof. Background technique [0002] A great feature of non-volatile memory element design is the ability to preserve the integrity of the data state when the memory element loses or removes power. Currently, many different types of non-volatile memory devices have been proposed in the industry. However, related companies are still developing new designs or combining existing technologies to stack memory cell planes to achieve a memory structure with higher storage capacity. For example, some three-dimensional stacked NAND gate (NAND) flash memory structures have been proposed. [0003] As the size of the device shrinks, the gate pitch in the array area (ar...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/115H01L21/8247H10B69/00
Inventor 赖二琨施彦豪
Owner MACRONIX INT CO LTD
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