Fractional frequency division circuit and method based on programmable continuous mode changing frequency divider

Abstract

The invention discloses a fractional frequency division circuit based on a programmable continuous mode changing frequency divider. The fractional frequency division circuit comprises an FPGA circuit and the programmable continuous mode changing frequency divider. A sigma-delta modulator is arranged in the FPGA circuit to generate a modulation signal. The frequency dividing ratio is changed by controlling the programmable continuous mode changing frequency divider through a mode line; the programmable continuous mode changing frequency divider carries out frequency dividing on an input signal and the input signal is divided into two paths, wherein one path of signal serves as a fractional frequency divider output signal and the other path of signal serves a control clock of the sigma-delta modulator and is input into the FPGA circuit. According to the fractional frequency division circuit based on the programmable continuous mode changing frequency divider, fractional frequency division can be performed on the input signal of DC-14GHz with the fractional frequency division circuit and the frequency of the output signal can reach the maximum 270MHz. The ordinary FPGA circuit can be enough to carry out fractional frequency division and used in a fractional phase-locked loop, so that the phase demodulation frequency can be greatly improved, and therefore phase noise output by the fractional phase-locked loop is lowered.

Description

technical field [0001] The invention relates to the technical field of testing, in particular to a fractional frequency division circuit and a fractional frequency division method. Background technique [0002] With the development of microwave technology, the requirements for the phase noise of microwave test signals are getting higher and higher, and there is an urgent need to study low-noise frequency synthesis technology, and phase-locked loop is one of the main methods of frequency synthesis at present. An effective way to improve the phase noise of the PLL output is to increase the phase detection frequency. Increasing the phase detection frequency means increasing the input signal frequency of the fractional frequency division circuit, which requires the fractional frequency division circuit to perform fractional frequency division processing on high-frequency signals. [0003] figure 1 Shown is the schematic diagram of the existing fractional frequency division circ...

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Problems solved by technology

[0005] The present invention proposes a fractional frequency division circuit and method based on a programmable continuous modulus frequency divider, which solves the problem that a high-speed FPGA circuit is required when the existing fractional frequency division circuit is used in a high-discrimination phase-locked loop

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