An All-Digital Successive Approximation Register Type Fast-Locking Delay-Locked Loop

Abstract

The invention discloses a full-digital successive approximation register type rapid-locking delay lock ring. A circuit structure is characterized in that a numerical control delay chain capable of being reset is used for reducing the frequency dividing ratio between an input clock and a controller working clock to 1, the 2-b successive approximation register algorithm is used for reducing the searching cycle index by 50%, and therefore the purpose of rapid locking is achieved. Circuits comprise a front end circuit, a numerical control delay chain, a phase synthesis circuit, a 2-b successive approximation register controller, a phase judging circuit and a reset pulse generating circuit. As is shown in the experiment results, according to the circuits, the locking frequency range is from 100MHz to 400 MHz, the locking time is 5 clock periods, clock signals of 50% duty ratio are output after locking, and harmonic wave locking is prevented.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to a digital integrated circuit clock synchronization module. Background technique [0002] The demand of human beings for low power consumption and high-performance electronic products has promoted the continuous advancement of the semiconductor process level, which has continuously improved the design technology of integrated circuits. Reusable modules such as silicon intellectual property (Intellectual Property, IP) cores have been widely used in the design, and integrated technology and IP cores have been combined to shorten the design cycle of the System on Chip (SoC) as much as possible. At the same time, SoC chips are also developing in the direction of multi-core and multi-clock domains, and the complexity of the chip's internal clock architecture is increasing day by day. Today's mainstream processor cores have an on-chip clock frequency of GHz, and there are multi...

AI Technical Summary

Problems solved by technology

[0006] The traditional all-digital successive approximation register (SAR) delay-locked loop has problems such as too long lock time, harmonic lock and deadlock, which greatly limit its application in practical systems

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