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DIBR (depth image based rendering) system realized on basis of hardware

A technology with hardware implementation and effective data, applied in the field of 3D TV, can solve problems such as large demand for hardware resources and complex system, and achieve the effects of reducing computational complexity, complexity and hardware overhead.

Inactive Publication Date: 2014-01-22
SICHUAN PANOVASIC TECH +1
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Problems solved by technology

The hardware implementation of this algorithm can support real-time processing of 1080p video, but the whole system is still very complicated, and the hardware resource requirement (hardware resource requirement) is also relatively large

Method used

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  • DIBR (depth image based rendering) system realized on basis of hardware
  • DIBR (depth image based rendering) system realized on basis of hardware
  • DIBR (depth image based rendering) system realized on basis of hardware

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Embodiment Construction

[0038] Specific embodiments of the present invention will be described below in conjunction with the accompanying drawings, so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when detailed descriptions of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

[0039] figure 1 It is a principle diagram of a specific embodiment of the DIBR system implemented based on hardware in the present invention.

[0040] In this example, if figure 1 As shown, the DIBR system implemented based on hardware of the present invention includes a parameter setting module 1, a valid data signal extension module 2, a three-dimensional image transformation module 3, a value filtering module 4 in a disparity map, a hole filling module 5, a pixel copy module 6 and a top layer Block RAM (D 0 ) 7. In the present embodiment, the DIBR system implemented ...

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Abstract

The invention discloses a DIBR (depth image based rendering) system realized on the basis of hardware. A three-dimensional image conversion algorithm which does not require camera parameters is adopted for replacing complicated homograph, and a hole filling algorithm based on a disparity map is adopted for replacing an image repairing algorithm, so the calculation complexity is greatly reduced. Meanwhile, the line grade flow line processing is adopted, and the storage of the disparity map and reference images is reduced, so the expenditure of the hardware is saved. The testing is carried out on a Xilinx Virtex TM-5 development board. Experiment results show that because the calculation complexity is reduced, during the real-time processing on full-high-definition videos, the throughput capacity can reach 60 frames / second, the real-time processing on the full-high-definition (1080P) videos can be supported, in addition, the hardware expenditure (not including an internal memory) is 59.8K logic gate, the capacitance requirement of the internal memory is 20.25k bytes, the hardware expenditure is reduced, and the synthesis results are similar to the DIBR algorithm.

Description

technical field [0001] The invention belongs to the technical field of 3D television, and more specifically relates to a hardware-based DIBR system. Background technique [0002] With the rapid development and popularization of 3D display technology and 3D TV system, view synthesis engine (view synthesis engine) has become an important part of synthesizing single-viewpoint or multi-viewpoint video in 3D TV and free viewpoint television. The core algorithm currently used in the view synthesis engine is based on the depth-image-based rendering (DIBR) algorithm. [0003] The DIBR algorithm is based on 3D image warping, and realizes the function of generating an image of another viewpoint from one or more images and their corresponding depth maps. The view synthesis engine using the DIBR algorithm only needs to transmit one channel of video and the corresponding depth map to obtain stereo image pairs (stereo pairs), thereby reducing the transmission bandwidth. At the same time...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N13/00G06T15/00
Inventor 刘然谭伟敏黄振伟田逢春李博乐曹东华谭迎春
Owner SICHUAN PANOVASIC TECH
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