Method for preparing semiconductor substrate with cavity

Abstract

The invention provides a preparation method of a semiconductor substrate with a cavity. The preparation method comprises the following steps: a first substrate and a second substrate are provided, wherein the first substrate comprises a support layer, an oxidation layer on the surface of the support layer and a device layer on the surface the oxidation layer; the graphical cavity is formed on the surface of the second substrate; an insulating layer / insulating layers is / are formed on the surface / surfaces of the second substrate or / and the device layer; the first substrate and the second substrate are bonded together by taking the insulating layer and the device layer as middle layers; the annealing is performed on the bonded substrate; the mechanical lapping is performed on the support layer of the first substrate so as to reduce the thickness of the support layer, and the support layer with the thickness more than 5 um is reserved; the chemically mechanical polishing is performed on the support layer of a reserved part so as to completely remove the support layer of the reserved part; the oxidation layer is removed through corrosion so as to form semiconductor substrate with the cavity. The preparation method has the advantage that the combination method of the mechanical lapping, the chemically mechanical polishing and the corrosion is adopted, so that the crush of a top layer and a silicon layer due to only partial support during the process of mechanical lapping is prevented.

Description

technical field [0001] The invention relates to a method for preparing a silicon-on-insulator substrate, in particular to a method for preparing a semiconductor substrate with a cavity. Background technique [0002] The MEMS processing technology of silicon microstructure absorbs and integrates other processing technologies to realize various micromechanical structures. With the development of MEMS technology, Cavity-SOI material (silicon on insulator with cavity) has been used more and more in MEMS devices such as pressure sensors and gyroscopes. Bonding and Backside Thinning (BESOI) technology is currently the most mature and commercialized SOI technology: two oxidized silicon wafers are used as the support substrate and the device substrate respectively, and then bonded together at a temperature higher than 1000 ° C. Reinforce at high temperature for more than 2 hours, and then use grinding, polishing, etc. to thin the device substrate to the thickness required by the SO...

AI Technical Summary

Problems solved by technology

[0003] Under the conventional BESOI thinning process, the top silicon thickness of Cavity-SOI is difficult to break through the limit of 5 μm, and good uniformity cannot be guaranteed; therefore, some SOI materials with thin top silicon thickness are required (such as high-end capacitive pressure sensors, SOI The top silicon thickness of the material is required to be less than 3 μm), and a new preparation process is required

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