Computing core and its instruction management method

Abstract

Disclosed are an operation core and an instruction management method thereof. The instruction management method includes receiving and storing an instruction of an instruction block, wherein the instruction block is present; operating the stored instruction of the instruction block. By the operation core and the instruction management method thereof, instruction off-target and waiting delay of the operation core are effectively reduced, and calculating efficiency of the operation core is improved.

Description

technical field [0001] The invention relates to the technical field of instruction management, in particular to an instruction management method of an operation core and an operation core. Background technique [0002] In a general-purpose processor, a hierarchical instruction storage structure is generally adopted, that is, instructions are stored in storage media of different levels. The computing core (the component device of the processor, each computing core can be regarded as a small processor) obtains instructions from the local memory during execution. Due to the limited local memory capacity of the computing core, it is easy to fail to fetch instructions. That is to say, if the instruction to be executed is not stored in the operation core, the operation core needs to obtain the instruction from the upper-level instruction memory before continuing to execute. Failure to fetch instructions is also called instruction miss. In the case of a hierarchical instruction st...

AI Technical Summary

Problems solved by technology

[0011] However, SIMD technology requires each instruction of each computing core to be executed synchronously, and the resources of the computing core are usually difficult to be fully utilized, and the computing power of all computing cores cannot be utilized, which limits the scope of application of the technology.

[0012] In multi-core and many-core processors, as the number of computing cores increases, the memory capacity in the computing cores is small. If the SPMD program size is greater than the memory capacity in the computing cores, frequent instruction fetching operations will still occur if the instruction fetch misses the target. Operational conflicts are intensified, communication network congestion is serious, and the waiting time for fetching instructions of the computing core is longer, which has a great impact on the computing efficiency of the computing core

Therefore, in multi-core and many-core processors, the memory capacity in the computing core limits the scope of application of SPMD technology

[0013] The method in the Chinese patent with publication number CN1466716A can only provide instruction prefetch service for one processor, and is not suitable for the processor structure of multi-core and many-core processors

On the other hand, the method for prefetching instructions in this patent requires an additional auxiliary processor for each computing core to execute a simplified version of the program, and the hardware overhead is large

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