Efficient fetch production line supporting synchronous EDAC inspection

Abstract

The invention discloses an efficient fetch production line supporting synchronous EDAC inspection. The procedure comprises the steps: (1) program address generate (AG), (2) program address send (AS), wherein the AS is used for receiving returned data from a Tag body, conducting hitting judgment, conducting Tag body accompany computation, judging whether errors occur in the Tag body and correcting the first stage errors, the production line is stopped when errors occur in the Tag body information which is received by the AS, the AS corrects the errors, then conducts the hitting judgment and judges whether to read a next stage memorizer or not, (3) program access ready wait (WT), wherein the WT is used for waiting for an instruction packet returned from a data body or the next memorizer, making judgment, conducting data body accompany computation, judging whether errors occur in the data body, correcting the first stage error and writing in the EDAC codes of the Tag body and the data body, and (4) program fetch packet receive (RE). The efficient fetch production line supporting synchronous EDAC inspection has the advantages of being efficient, strong in error correcting capability, little in hardware cost, transparent to a programmer and the like.

Description

technical field [0001] The present invention mainly relates to the design field of processors, in particular to a high-efficiency instruction fetch pipeline supporting synchronous EDAC verification, especially suitable for processors in the space field, that is, processors that need to check and correct the contents of the program memory Instruction fetch pipeline design technology. Background technique [0002] With the continuous deepening of human exploration of space, the impact of space radiation effects on electronic equipment in aircraft continues to intensify. On-board processors (including on-board CPU and DSP, etc.) are the core components of space vehicle electronic equipment, and it is of special significance to strengthen them against radiation. In the onboard processor, the single event upset (Single Event Upset, SEU) caused by the space radiation of the instruction cache (including the tag body and the data body) will cause a certain bit of its stored content...

AI Technical Summary

Problems solved by technology

[0004] In addition, the Cell unit of the on-chip memory is affected by the radiation effect and generally produces steady-state errors

Once this kind of error occurs, it is difficult to recover unless it is corrected

However, the read and write circuit of the on-chip memory is mainly composed of non-latch logic, which is prone to dynamic errors due to radiation effects, and the timing of such dynamic errors is uncertain.

If a steady-state error occurs in the Cell unit in the read data of a certain beat, and a dynamic error occurs in the read-write circuit, a 2-bit error is likely to occur, resulting in an error that cannot be recovered

The traditional instruction fetch pipeline design that supports EDAC often ignores the phenomenon that the read and write circuits are prone to dynamic errors, resulting in unsatisfactory error correction effects and low execution efficiency of the pipeline.

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