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Semiconductor device

A technology of semiconductors and transistors, applied in the field of semiconductor devices, can solve the problems of ESD protection function damage, current concentration, cost increase, etc.

Inactive Publication Date: 2013-07-24
SEIKO INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Therefore, there is a problem that the area occupied by the cut-off transistor is large, especially in a small IC chip, which becomes a cause of an increase in the cost of the entire IC.
[0006] In addition, an off transistor usually adopts a combination of a plurality of drain regions, source regions, and gate electrodes in a comb shape. However, by combining a plurality of transistors, there are cases where it is difficult to make an N-type MOS for ESD protection The transistor operates uniformly as a whole. For example, current concentration occurs in the part close to the external connection terminal, and the original ESD protection function cannot be fully exerted and is destroyed.

Method used

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  • Semiconductor device
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Embodiment 1

[0019] 1 is a schematic cross-sectional view showing a first embodiment of an N-type MOS transistor for ESD protection of a semiconductor device according to the present invention.

[0020] On a P-type silicon substrate 101 that is a semiconductor substrate of the first conductivity type, a source region 201 and a drain region 202 composed of a pair of N-type high-concentration impurity regions are formed, and are formed between other elements. The trench isolation region 301 of shallow trench isolation is used for insulation isolation.

[0021] Between the source region 201 and the drain region 202, in the upper part of the channel region of the P-type silicon substrate 101, a gate insulating film 401 made of a silicon oxide film or the like is formed and formed of a polysilicon film or the like. The gate electrode 402. Here, a trench isolation region 302 for ESD protection is formed in a region in contact with the drain region 202, and the depth in the vertical direction of...

Embodiment 2

[0027] 2 is a schematic cross-sectional view showing a second embodiment of an N-type MOS transistor for ESD protection of a semiconductor device according to the present invention.

[0028] The difference from the first embodiment shown in FIG. 1 is that the corners of the bottom surface of the ESD protection trench isolation region 302 in which the drain extension region 203 is formed are rounded to form a rounded trench isolation. Area bottom surface 801 .

[0029] When a large forward current is applied from the outside, the current applied as the forward current of the diode caused by the junction of the N-type of the drain region of the N-type MOS transistor 601 for ESD protection and the P-type of the substrate is released. In this case, the effective drain region of the N-type MOS transistor 601 for ESD protection becomes the region combining the drain region 202, the drain extension region 203, and the drain contact region 204. However, as shown in FIG. The shape of ...

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Abstract

In the semiconductor device including an ESD protection N-type MOS transistor which reduces increase of occupied area and has a sufficient ESD protective function, a drain region of the ESD protection N-type MOS transistor is electrically connected to a drain contact region via a drain extended region. The drain extended region is provided on a side surface and a lower surface of an ESD protection trench isolation region, and is formed of an impurity diffusion region of the same conductivity type as that of the drain region. The drain contact region is formed of an impurity diffusion region of the same conductivity type as that of the drain region.

Description

technical field [0001] The present invention relates to a semiconductor device having an ESD protection element between an external connection terminal and an internal circuit area, and the ESD protection element is formed to protect internal elements formed in the internal circuit area from being destroyed by ESD. Background technique [0002] In a semiconductor device having a MOS transistor, it is known to fix the gate potential of the N-type MOS transistor to ground ( Vss) and set to the off state, so-called cut-off transistors. [0003] In order to prevent ESD destruction of internal circuit components, it is important to introduce as large a proportion of static pulses as possible into the cut-off transistors and not propagate them to internal circuit components, or to change fast and large static pulses into slow and small ones. The signal is then transmitted. [0004] In addition, unlike the MOS type transistors constituting other internal circuits such as logic ci...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02
CPCH01L29/0847H01L29/7835H01L27/0266H01L27/0617H01L29/0653H01L27/04
Inventor 鹰巢博昭
Owner SEIKO INSTR INC
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