Wafer level semiconductor encapsulation structure with stacking chips and manufacturing method thereof

Abstract

The invention provides a wafer level semiconductor encapsulation structure with stacking chips and a manufacturing method of the wafer level semiconductor encapsulation structure. The wafer level semiconductor encapsulation structure comprises a first chip, a plurality of wire frame terminals, a second chip and encapsulation colloid, wherein the first chip is provided with a downward active surface, the wire frame terminals surround the first chip, the second chip is stacked on the first chip in an insulation mode and provided with an upward active surface, the active surface of the second chip is electrically connected to the wire frame terminals through metal wires, the encapsulation colloid covers the first chip, the wire frame terminals and the second chip, and the active surface of the first chip and the bottom faces of the wire frame terminals are exposed. According to the wafer level semiconductor encapsulation structure with the stacking chips, chip stacking is achieved through connection of the wire frame terminals and the metal wires, the size of a product and structural stress can be effectively reduced.

Description

technical field [0001] The invention relates to a semiconductor packaging structure, in particular to a wafer-level semiconductor packaging structure with stacked chips and a manufacturing method thereof. Background technique [0002] In the general wafer-level packaging manufacturing process, the packaging operation is performed directly on the wafer, and then the wafer is cut to complete the production of the semiconductor chip packaging structure. Since wafer-level packaging can complete all component assembly processes before wafer dicing, it can effectively reduce the cost of the entire product process cycle, and can achieve smaller-sized packaging to meet the requirements of light, thin and short, and its electrical connection On the one hand, it has shorter transmission lines, so wafer-level packaging is a packaging method that can effectively save space and cost. [0003] To meet design requirements, the current fan-out wafer-level (Fan out WLP) semiconductor packag...

AI Technical Summary

Problems solved by technology

Among them, the method of arranging chips side by side will lead to a large increase in the horizontal size of the packaged product and its packaging structure will be affected by greater stress; Silicon via) manufacturing process, so that the upper chip can be electrically connected to the underlying circuit of the lower chip through the via hole, the disadvantage of this method is that the cost of the through hole forming process is too high

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