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In-situ tensile sample preparation method for mechanical performance testing of tsv copper interconnection materials

A technology of material mechanics and in-situ stretching, which is applied in the field of in-situ stretching sample preparation for mechanical performance testing of TSV copper interconnect materials, can solve problems such as inability to infer the properties of tiny samples, and achieve convenient and effective tensile strength and manufacturing methods simple effect

Active Publication Date: 2015-08-05
NAT CENT FOR ADVANCED PACKAGING CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the size of the copper pillar is only micron, and its mechanical properties are very different from those of the macroscopic bulk material. The properties of the tiny sample cannot be inferred from the mechanical parameters such as the elastic modulus and tensile strength of the bulk material.

Method used

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  • In-situ tensile sample preparation method for mechanical performance testing of tsv copper interconnection materials
  • In-situ tensile sample preparation method for mechanical performance testing of tsv copper interconnection materials
  • In-situ tensile sample preparation method for mechanical performance testing of tsv copper interconnection materials

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Embodiment Construction

[0019] The present invention will be further described below in conjunction with drawings and embodiments.

[0020] Such as Figure 6 As shown, the in-situ tensile sample produced by the present invention includes a TSV copper column 2 , a silicon wafer 1 at both ends of the copper column and a sample clamping end 5 . The specific preparation method is as follows:

[0021] one. Prepare a silicon wafer filled with TSV copper plating, such as figure 1 shown. The silicon wafer thickness is 200-500μm. TSV via holes have a diameter of 20-50 μm and a height of 200-500 μm.

[0022] two. right figure 1 The silicon wafer is diced, so that there is at least one TSV copper pillar 2 ( figure 2 1 in the middle), and fix the silicon chip 1 on the carrier 3, such as figure 2 As shown; the carrying device 3 has a groove structure, and the size of the groove is the same as the size of the cut silicon wafer. The upper surfaces of the silicon wafers are on the same plane, and the TSV...

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Abstract

The invention discloses a preparation method of an in-situ tensile sample for a TSV (through-silicon-via) copper-interconnection material mechanics performance test. The in-situ tensile sample comprises a TSV copper pillar, silicon slices arranged at two ends of the copper pillar and a clamping end; and the preparation method comprises the following steps of: firstly, cutting and fixing a silicon wafer with a TSV through hole / blind hole structure, then photo-etching and etching silicon slices to expose the middle part of the TSV copper pillar, and finally fixing the silicon slices at two ends of the TSV copper pillar to the clamping end, so as to form the in-situ tensile sample. The preparation method disclosed by the invention is simple, can conveniently and effectively performs the tensile performance test of the in-situ TSV copper pillar, solves the problem that both block and film samples cannot reflect the true mechanics performance of the micro-size TSV copper-interconnection material, and can provide effective data support for the reliability of the TSV.

Description

technical field [0001] The invention relates to the field of microelectronic packaging, in particular to an in-situ tensile sample preparation method for testing the mechanical properties of TSV copper interconnection materials. Background technique [0002] With the continuous improvement of the integration level of semiconductor circuits, the electronic packaging density is also increasing. In recent years, the three-dimensional packaging form that stacks multiple chips in the height direction and realizes electrical connection through silicon via (TSV) technology has developed rapidly and has become a new generation of electronic packaging technology. In this packaging structure, by stacking two or more layers of chips, not only can the integration of the circuit be greatly improved, but also the transmission distance of the circuit can be reduced, which is conducive to improving the integrity of the signal and reducing the loss of the signal. [0003] During the chip pa...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01N1/28
Inventor 于大全刘海燕
Owner NAT CENT FOR ADVANCED PACKAGING CO LTD
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