Bit-plane coding hardware structure and method in compliance with ccsds standard

Abstract

The invention discloses a bit plane encoding hardware structure and a method according with the consultative committee for space data system (CCSDS) standard. The bit plane encoding hardware structure comprises a scanning module, a position memory, a bit plane encoding module and a code stream organization module. The bit plane encoding method specifically includes the following steps: step 1, receiving wavelet coefficient data; step 2, providing position information; step 3, scanning importance information; step 4, generating coefficient numbers; step 5, mapping sign values; step 6, computing encoding methods; step7, entropy coding; and step 8, outputting generated code stream. According to the bit plane encoding hardware structure and the method according with the CCSDS standard, the method of acquiring importance information by 'or' operation is adopted, and computation complexity is reduced; the read-only memory (ROM) is adopted to achieve mapping encoding, and therefore hardware resource cost is reduced; and a parallel stream structure is adopted, the method that a plurality of bit planes use the same mapping encoding module repeatedly is used, and therefore the defects that encoding efficiency is low and hardware resource cost is large in the prior art are overcome, and bit plane encoding can be achieved in a high-efficiency and low-resource mode.

Description

technical field [0001] The invention belongs to the technical field of communication, and further relates to a bit-plane encoding hardware structure and method in the technical field of image processing in compliance with the CCSDS (Consultative Committee for Space Data Systems) image compression standard. The invention can realize the bit plane coder with high efficiency and low resources, and is suitable for the image compression system of aerospace. Background technique [0002] The CCSDS image compression method is widely used in the field of image compression. For the image data compression standard CCSDS122.0-B-1, the algorithm description uses a serial encoding method for each bit plane. If the hardware encodes according to the serial method, then The coding efficiency of the system is low, which cannot meet the high throughput requirement of the satellite image compression system. [0003] The patent "An image lossless compression processing system and method confor...

AI Technical Summary

Problems solved by technology

The shortcoming of this patent application device is: adopt the serial coding mode, the coding rate is low

The disadvantage of the method of this patent application is: the implemented method only supports the lossless compression of images, and cannot perform lossy image compression processing

The disadvantage of the coding structure of this patent application is that each part of the coding is completed sequentially by means of state machine jumps, and the coding efficiency is low

The disadvantage of this patent application method is: only the rate optimization method for data reception and transmission is adopted, and the implementation method of the bit-plane coding part in the CCSDS coding system is not mentioned

This structure uses a parallel processing method for bit-plane scanning, but in the subsequent bit-plane encoding module, sequential encoding is still used, which severely limits the encoding efficiency

The disadvantage of this FPGA implementation method is that the hardware resources are not reasonably allocated for the internal structure of the FPGA, resulting in a large hardware resource overhead

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