Bipolar circuit manufacture method

Abstract

The invention provides a bipolar circuit manufacture method. The bipolar circuit manufacture method includes: depositing a first dielectric layer on a provided semiconductor substrate, and forming doped deep phosphorus, a first-type doped region, a second-type doped region and upper isolation in an epitaxial layer of the semiconductor substrate; combining a contact hole pattern and a capacitive window pattern on a same mask for etching, forming contact holes in the first dielectric layer formed at each level, and forming a required capacitive window in the first dielectric layer on the second-type doped region; and growing a silicon dioxide layer, removing the silicon dioxide layer in part of the selected capacitive window and removing part of the deposited silicon nitride layer to keep the silicon nitride layer in the required capacitive window so as to form different capacitance. The bipolar circuit manufacture method is capable of shortening production time of an annealing process in an emitter region, meets the requirements of high and low voltage modules in a special circuit on capacitance value and capacitive withstood voltage and weakens influences of the emitter region and contact hole photoetching alignment precision on products.

Description

technical field [0001] The invention belongs to the technical field of semiconductor manufacturing technology, and in particular relates to a manufacturing method of a bipolar circuit. Background technique [0002] Traditional bipolar circuit technology employs manufacturing methods combined with flow Figure 1 to Figure 8 To give a detailed explanation: [0003] see figure 1 , forming the bottom layer: select a suitable substrate material 21; form the N-type doped buried layer 22 and the P-type doped lower isolation required for the circuit on the substrate material through oxidation, photolithography, etching, implantation and other processes 23; generate epitaxial layer 24 by epitaxial process; oxidation generation The first oxide layer 26 is used to block the regions that do not need to be doped; a deep phosphorus window is formed in the epitaxial layer 24 by photolithography and etching processes, and is formed by phosphorus diffusion doping, annealing and oxidation...

AI Technical Summary

Problems solved by technology

Each layer of graphics has a special function, and there are fixed size and tolerance regulations. There will be a registration tolerance in the process of registering these graphics with each other to form a circuit through the photolithography process. If the registration deviation exceeds the tolerance of the graphics Poor, it is bound to affect the circuit parameters

The deviation between the two layers of the emitter region and the contact hole of the NPN transistor will cause a short circuit between the emitter region and the base region, resulting in poor electrical properties

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