Method for manufacturing fin field effect transistor (FET)

Abstract

The invention discloses a method for manufacturing a fin field effect transistor (FET). Polycrystalline silicon layers are deposited on two fin structures of the FinFET twice, a height difference is correspondingly formed above the two fin structures, polycrystalline silicon is etched back by means of the height difference, a gate of one fin structure is divided to form two gates for further formation of a 4T-FinFET, the 4T-FinFET and a 3T-FinFET can be integrated to be manufactured, etching precision can be accurately controlled, damage to a device structure is avoided, and self-alignment is achieved during manufacturing.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, and more particularly, to a method for preparing a fin field effect transistor. Background technique [0002] In the process of seeking higher device density, higher performance, and lower cost, as the integrated circuit process continues to develop to the nanotechnology process node, some manufacturers have begun to consider how to move from planar CMOS transistors to three-dimensional fin field Transition issues in effect transistor (FinFET) device structures. FinFET is a new type of complementary metal-semiconductor (CMOS) transistor, which can adjust the threshold voltage of the device according to needs, and further reduce static power consumption (static power consumption). Compared with planar transistors, FinFET devices reduce short-channel effects due to improved control of the channel. [0003] Currently, FinFETs generally include three-terminal FinFETs (3terminal ...

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Problems solved by technology

However, this method is a huge challenge for the self-alignment requirements during lithography, which will increase the difficulty of the process

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