On-chip network node communication method based on macro virtual channel

Abstract

The invention discloses an on-chip network node communication method based on a macro virtual channel, and relates to the field of the communication methods between on-chip network nodes, so that information transmission errors caused by the errors of input caches inside the communication nodes are avoided. The method is realized through the following process that a data packet from another communication node enters a route of a communication node; two copies of the data packets with a reliability requirement are prepared; the data packets with the reliability requirement and the two copies of backup data thereof respectively enter virtual channels of the input caches; the data packets with the reliability requirement and the two copies of backup data thereof send application signals to a virtual channel distributor; if the application is approved, the data packets with the reliability requirement and the two copies of backup data thereof respectively enter the macro virtual channel; in the macro virtual channel, a principle that the minority is subordinate to the majority is followed and a correct data packet is determined; the macro virtual channel is a virtual channel of three specified addresses in the input caches; and the obtained correct data packet is transmitted to the next communication node through an output channel.

Description

technical field [0001] The invention relates to a communication method between nodes of an on-chip network. Background technique [0002] With the development of integrated circuits, there are three major problems in the system-on-chip (SoC, System on Chips) based on traditional bus interconnection: the scalability problem caused by limited address space, the communication efficiency problem and the area and area caused by global synchronization. power consumption problem. Network on Chip (NoC, Network on Chips) attempts to solve these problems from the architecture, and will become the mainstream design technology of the next generation of integrated circuits. However, in the deep sub-micron stage, due to the shrinking chip size and increasing number of devices, data packets are more susceptible to electromagnetic interference during the transmission of the network on chip, resulting in errors such as single event flips. Alpha particles emitted by trace amounts of uranium...

AI Technical Summary

Problems solved by technology

[0002] With the development of integrated circuits, there are three major problems in the system-on-chip (SoC, System on Chips) based on traditional bus interconnection: the scalability problem caused by limited address space, the communication efficiency problem and the area and area caused by global synchronization. power consumption problem

However, in the deep sub-micron stage, due to the shrinking chip size and the gradually increasing number of devices, data packets are more susceptible to electromagnetic interference during the transmission of the network on chip, resulting in errors such as single event flips.

Images