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Circuit for harmonizing read and wright between central processor and input output interface device

A central processing unit, input and output technology, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of reading or writing data errors, too late to send waiting signals, and impracticality, so as to avoid transmission errors and reduce The effect of system design

Inactive Publication Date: 2003-07-02
CAMEO COMM
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] 1. Because it is too late to issue a waiting signal that is not yet ready, it often causes erroneous actions to read or write data
[0007] 2. When trying to achieve synchronization or handshake, it actually increases the troubles in system design
[0008] 3. Not practical
[0009] 4. Not progressive
[0010] 5. Lack of industrial competitiveness

Method used

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  • Circuit for harmonizing read and wright between central processor and input output interface device
  • Circuit for harmonizing read and wright between central processor and input output interface device
  • Circuit for harmonizing read and wright between central processor and input output interface device

Examples

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Embodiment Construction

[0039] see Figure 6 Shown, the present invention is to set up a synchronous control unit 3 and a signal input unit 5 (referring to Fig. 7, shown in 8) between CPU (central processing unit) 1 and PCMCIA Card (standard input and output interface device) 2, wherein the The synchronous control unit 3 may include:

[0040] A flip-flop 31, the input terminal is connected to the output terminal of a read-write signal extractor 32, and the reverse output terminal is connected to one input terminal of the first comparison logic gate 33, and the input terminal is controlled by the trigger terminal. When the connected CPU (Central Processing Unit) 1 is input with timing pulse (Clock) 4, the reverse output terminal can provide a reverse sync pulse state.

[0041]A read-write signal picker 32, the input end is respectively connected with the signal control lines of the read end (READ) and the write end (WRITE), and the output end is connected to the input end of a flip-flop 31, when Whe...

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Abstract

A circuit for coordinating the R / W operation between CPU and I / O interface is a synchronization controller connected between them. When a R / W request is sent from CPU to I / O interface and the I / O interface is not ready, its sents a synchronous wait compensating signal to CPU to make it in waist state until the I / O interface is ready. Then R / W operation is conducted.

Description

technical field [0001] The invention relates to a computer circuit, in particular to a circuit for coordinating reading and writing between a central processing unit and an input and output interface device. Background technique [0002] figure 1 What is shown is an example of data transmission between a general CPU (central processing unit) 1 and a PCMCIA Card (standard input and output interface device). [0003] Wherein when the CPU (central processing unit) 1 transmits data to the peripheral equipment, the PCMCIA Card (standard input and output interface device) addresses and assembles the data through the DATA BUS (data bus) and ADDRESS BUS (address bus), and through The Chip Select (component selection signal line), READ / WRITE (read-write control line) and WAIT (wait signal) lines of the CONTROL BUS (control bus) are used to control the direction of data transmission and whether to open or not. When the peripheral equipment is not ready When the PCMCIA Card (standard...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/42
Inventor 吴铭修
Owner CAMEO COMM
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