Circuit for harmonizing read and wright between central processor and input output interface device

Abstract

A circuit for coordinating the R / W operation between CPU and I / O interface is a synchronization controller connected between them. When a R / W request is sent from CPU to I / O interface and the I / O interface is not ready, its sents a synchronous wait compensating signal to CPU to make it in waist state until the I / O interface is ready. Then R / W operation is conducted.

Description

technical field [0001] The invention relates to a calculator circuit, in particular to a circuit for coordinating reading and writing between a central processing unit and an input and output interface device. Background technique [0002] figure 1 What is shown is an example of data transmission between a general CPU (central processing unit) 1 and a PCMCIA Card (standard input and output interface device). [0003] Wherein when the CPU (central processing unit) 1 performs data transmission to the peripheral equipment, the PCMCIA Card (standard input and output interface device) addresses and assembles the data through the DATA BUS (data bus) and ADDRESS BUS (address bus), and Use the Chip Select (component selection signal line), READ / WRITE (reading and writing control line) and WAIT (waiting signal) lines of the CONTROL BUS (control bus) to control the direction of data transmission and whether to open or not. When ready, first send a wait signal to the CPU (central pro...

AI Technical Summary

Problems solved by technology

[0004] However, the PCMCIA Card (Standard Input Output Interface Device) 2 of general computer peripheral equipment is not as fast as the CPU (Central Processing Unit) 1 in execution speed. The speed has been greatly increased from the early 4MHZ and 8MHZ to the high-speed timing pulse (Clock) of hundreds of MHZ or even GHZ today. Therefore, when the high-speed CPU (central processing unit) 1 is connected to the low-speed PCMCIA Card (standard input and output interface device) ) 2 When requesting to read or write (READ / WRITE) data (see Figures 4 and 5 again), it is often easy to issue WAIT ( Waiting for signal) signal informs CPU (central processing unit) 1 that it is currently in an unready state (READ / WRITE or DATA has no signal coming in) and thus causes CPU (central processing unit) 1 to read or write at present The data are all incorrect data. The main reason is that the CPU (central processing unit) 1 cannot detect the waiting signal (taking the low potential trigger as an example) on the detection starting point A of the effective timing pulse, so that the detection cut-off point B cannot confirm in time whether it is necessary to continue sending WAIT (wait signal) requests, and directly executes the reading or writing action, resulting in data transmission errors. Therefore, for high-speed CPU (central processing unit) 1 and lower speed The synchronization (Synchronization) or processing (Handshaking) between the computer peripheral equipment, sometimes need to use cumbersome software calculations to control and eliminate the error between the speeds, and sometimes need to reduce the overall working timing of the system, but it will cause the overall system to work Poor efficiency and increased trouble in system design

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