High-speed data writing structure and writing method for phase change memory

Abstract

The invention discloses a high-speed data writing structure and a high-speed data writing method for a phase change memory. The high-speed data writing structure comprises a comparison circuit, a data storage unit with N data bits and a flag bit, (N+1) writing circuits and a control circuit; the comparison circuit is used for comparing data read from an array with data required for being written, and sending a comparison result to the control circuit; the first writing circuit of the (N+1) writing circuits is used for executing a SET / RESET operation on the flag bit of the data storage unit; the N writing circuits are respectively used for executing the SET / RESET operation on the N data bits of the data storage unit; and the control circuit is used for controlling the (N+1) writing circuits to execute different SET / RESET operations on the flag bit and the data bits according to the comparison result. By the adoption of the high-speed data writing structure and the high-speed data writing method, the data writing speed can be increased, and the power consumption is reduced.

Description

technical field [0001] The invention relates to a phase-change memory, in particular to a high-speed data writing structure and a writing method of the phase-change memory. Background technique [0002] Phase change memory (PRAM) is a commonly used storage device at present. Its main principle is that by applying special pulses of different sizes, the local area of ​​the phase change material will produce an amorphous state and a crystalline state due to different temperatures. The change. Generally, the amorphous state is used to represent logic "1", and the crystalline state represents logic "0" to store data. [0003] Compared with other dynamic memory (DRAM) and flash memory (Flash), PRAM has the following obvious advantages: [0004] 1. Low driving voltage; [0005] 2. Low power consumption; [0006] 3. Fast reading and writing speed; [0007] 4. PRAM is suitable for anti-radiation. [0008] In addition, using 28nm and below CMOS process, the performance of PRAM m...

AI Technical Summary

Problems solved by technology

[0015] In the design of modern PRAM, the current of SET and RESET of a single data bit of PRAM is reduced, but due to the need to increase the writing speed and write (or page mode) more data bits at the same time, when writing The peak current increases significantly, and the writing time increases significantly

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