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Recombination sequencing method of fast serial interface programmable communication interface-express (PCI-E) protocol completion with data (CplD)

A technology of PCI-E and serial interface, which is applied in the field of reorganization and sorting of fast serial interface PCI-E protocol data completion packets to achieve the effect of solving disorder

Active Publication Date: 2012-07-11
重庆重邮汇测电子技术研究院有限公司
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  • Claims
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Problems solved by technology

[0006] In order to solve problems such as the need for reorganization and sorting of data completion packets existing in the processing of PCI-E non-forwarding transactions implemented by FPGA in the prior art, the present invention proposes a fast serial interface PCI-E protocol data completion packet reorganization and sorting method

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  • Recombination sequencing method of fast serial interface programmable communication interface-express (PCI-E) protocol completion with data (CplD)
  • Recombination sequencing method of fast serial interface programmable communication interface-express (PCI-E) protocol completion with data (CplD)
  • Recombination sequencing method of fast serial interface programmable communication interface-express (PCI-E) protocol completion with data (CplD)

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Embodiment Construction

[0025] attached figure 1 It is the data buffer structural representation of fast serial interface PCI-E protocol data of the present invention to complete the reorganization sorting method of packet, among the figure, the left side is the data buffer unit, and the right side is the index number of the data buffer unit. As can be seen from the figure, the fast serial interface PCI-E protocol data of the present invention completes the reorganization sorting method of the packet, and the requester defines a data buffer in the memory, and it is divided into two or more than two data buffer units of the same size , the size of the data buffer unit is 128 bytes, and the size of the data buffer unit does not exceed 8K bytes. Each data buffer unit corresponds to an index number in sequence and only stores one data completion packet CplD; the requester will receive the MRd request The returned CplDs are sequentially stored in the data buffer unit; at the same time, according to the va...

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Abstract

In order to solve the problems that in the prior art, completion with data (CplD) needs the recombination sequencing in the processing process of programmable communication interface-express (PCI-E) non-posted type affairs realized by adopting a field programmable gate array (FPGA), and the like, the invention provides a recombination sequencing method of fast serial interface PCI-E protocol CplD. The method comprises the steps that: a requester defines a data buffer region in a memorizer, in addition, the data buffer region is divided into two or more than two data buffer units with the same size, and each data buffer unit sequentially corresponds to one index number and only stores one CplD; the received CplDs returned by memory read requests (MRd) are sequentially stored in the data buffer units; and meanwhile, the CplDs in the data buffer region are sequenced in the mode from smaller Tag values to greater Tag values, and a chain list management structure is adopted for realizing the dynamic building and updating. The recombination sequencing method has the beneficial effects that the requester receives the CplD, meanwhile, the CplD sequencing work can be carried out, and the CplD disorder problem is solved.

Description

[0001] technical field [0002] The invention relates to communication system data transmission technology, in particular to a fast serial interface PCI-E protocol data completion packet reorganization and sorting method. Background technique [0003] The fast serial interface PCI-E (PCI Express, referred to as PCI-E) is the bus interface of the new generation communication system. It uses serial, point-to-point interconnection to realize the communication between two devices, which can significantly improve the Data transmission rate, at present, its 2.0 version has increased the interface rate to 5Gbps. The PCI-E architecture adopts a layered design. From bottom to top, it is: physical layer, data link layer, transaction layer and software layer. Among them, the transaction layer is an important part of PCI-E design. The so-called PCI-E transaction is defined as "a sequence of occurrences consisting of one or several packets required to realize certain information between...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/56H04L49/901H04L49/9015
Inventor 梁燕王晓娇邵凯李志宽段文亮舒明华
Owner 重庆重邮汇测电子技术研究院有限公司
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