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Vertical parasitic PNP (plug-and-play) triode in BiCMOS (bipolar complementary metal oxide semiconductor) process and manufacturing method

A PNP triode and vertical parasitic technology, which is applied in semiconductor/solid-state device manufacturing, transistors, electrical components, etc., can solve the problems of large device area, large collector connection resistance, device size reduction, etc., and achieve large current amplification factor and reduce Resistor, the effect of increasing the current gain

Active Publication Date: 2012-07-11
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The disadvantage is that the device area is large and the connection resistance of the collector is large
Since the extraction of the collector electrode in the prior art is realized through another active region adjacent to the collector region, and the other active region and the collector region need to be isolated by STI or other field oxygen, such This greatly limits the further reduction of the device size

Method used

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  • Vertical parasitic PNP (plug-and-play) triode in BiCMOS (bipolar complementary metal oxide semiconductor) process and manufacturing method
  • Vertical parasitic PNP (plug-and-play) triode in BiCMOS (bipolar complementary metal oxide semiconductor) process and manufacturing method
  • Vertical parasitic PNP (plug-and-play) triode in BiCMOS (bipolar complementary metal oxide semiconductor) process and manufacturing method

Examples

Experimental program
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Embodiment B

[0045] like figure 1 Shown is a schematic structural view of the vertical parasitic PNP transistor in the BiCMOS process of the embodiment of the present invention. The vertical parasitic PNP transistor in the BiCMOS process of the embodiment of the present invention is formed on a P-type silicon substrate 1 and placed on the P-type silicon substrate 1. An N-type deep well 2 is formed on a silicon substrate 1, and the active region is isolated by a shallow trench field oxygen 3, which is shallow trench isolation (STI). The vertical parasitic PNP transistor includes:

[0046] A collector region, a P-type ion implantation region 7 is formed in each of the active regions, and the depth of the P-type ion implantation region 7 in each of the active regions is greater than or equal to the depth of the bottom of the shallow groove field oxygen 3 and connected to each other, the collector region is composed of a P-type ion implantation region 7 formed in the first active region. The ...

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PUM

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Abstract

The invention discloses a vertical parasitic PNP (plug-and-play) triode in a BiCMOS (bipolar complementary metal oxide semiconductor) process, a collector region is formed in a first active area; a pseudo buried layer is formed at the bottom of a shallow groove field oxide, transversely extends, enters into the first active area and is in contact with the collector region; the connection between the collector region and the adjacent active area is realized through the pseudo buried layer, and a collector is led out by forming metal contact at the top of the adjacent active area. N type polysilicon is formed at the upper part of a base region and a base is led out. An emitter region comprises a P type ion-implanted layer and a P type polysilicon formed above the base region. The invention further discloses a manufacturing method of the vertical parasitic PNP triode in the BiCMOS process. The vertical parasitic PNP triode disclosed by the invention can be used as an output device in a high-speed and high-gain BiCMOS circuit, one more device choice is provided for a circuit, the resistance of the collector of the PNP triode can be reduced, the frequency performance of the device can be improved, a polysilicon emitter can improve the gain of the device, and the production cost can also be reduced.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a vertical parasitic PNP transistor in a BiCMOS process, and also relates to a method for manufacturing the vertical parasitic PNP transistor in the BiCMOS process. Background technique [0002] In RF applications, higher and higher device characteristic frequencies are required. In BiCMOS process technology, NPN transistors, especially germanium-silicon heterojunction transistors (SiGe HBT) or germanium-silicon-carbon heterojunction transistors (SiGeC HBT) are good choices for UHF devices. And the SiGe process is basically compatible with the silicon process, so SiGe HBT has become one of the mainstreams of UHF devices. In this context, the requirements for the output device are correspondingly increased, such as having a current gain coefficient and a cutoff frequency not less than 15. [0003] In the prior art, the output device can adopt a verti...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/73H01L29/06H01L29/08H01L29/43H01L21/331
Inventor 刘冬华周正良钱文生董金珠
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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