Readout circuit and readout method for electrically erasable read-only memory

Abstract

The invention relates to a readout circuit and a readout method for an electrically erasable read-only memory. The readout circuit comprises a comparator, a reference resistor, a sensing resistor, a reference unit and a storage unit, wherein the readout circuit is only configured with one reference unit, and the same reference unit is used in the process of reading operation; the threshold voltage of the reference unit is set into neutral threshold voltage; and the voltage on a reference unit control grid is set into a fixed value, so that the configuration time in the manufacturing process is obviously reduced, and the threshold added on a storage unit control grid is changed along with operating modes. Meanwhile, the voltage added on the storage unit control grid during the reading operation and programming verification operation is lower than that in the prior art, so that a stress effect of grid voltage is reduced, and the threshold voltage of the reference unit is set to a value approaching the neutral threshold voltage so as to be more stable.

Description

technical field [0001] The invention relates to a readout circuit and a readout method for an electrically erasable read-only memory. Background technique [0002] A conventional Flash EEPROM (Electrically Erasable Read Only Memory) contains several memory cells. This memory cell is fabricated on a P-type semiconductor substrate, and each cell includes an n+ type drain terminal and an n+ type source terminal. There is a relatively thin gate dielectric layer on the substrate, above which is a floating gate formed of polysilicon. On the floating gate is a second dielectric layer, and on the second dielectric layer is a control gate formed of polysilicon. The channel region on the substrate isolates the source and drain terminals. [0003] The amount of charge on the floating gate is determined by the number of electrons contained in the floating gate. During programming, electrons are injected into the floating gate, which raises the threshold voltage of the memory cell. ...

AI Technical Summary

Problems solved by technology

Therefore, the configuration process consumes more time and increases costs

[0022] 2. Due to the reference cell Q used for programming verification and over-erasing verification R2 and Q R4 The threshold and neutral threshold UV_VT (neutral threshold refers to the threshold when there is no charge in the floating memory cell, the neutral threshold varies with the manufacturing process, the typical value of NOR Flash memory may be distributed between 2.3-3.5V) The deviation is large, so charge loss is prone to occur in the presence of disturbances, resulting in threshold shifts, which in turn affect the programmed threshold distribution and data retention time

Images