Wafer-level packaging method

Abstract

The invention relates to a wafer-level packaging method, which comprises the steps of sequentially forming a heat-resistant metal layer and a metal wetting layer on the pad and the passivation layer of a chip; forming photoresist on the metal wetting layer, wherein the photoresist is provided with an opening for exposing the metal wetting layer above the pad of the chip; forming a connecting layer on the metal wetting layer in the opening; removing the photoresist; etching the heat-resistant metal layer and the metal wetting layer on the passivation layer till the passivation layer is exposed; forming a protection adhesive layer on the chip, wherein protection adhesive covers the connecting layer; exposing the protection adhesive above the connecting layer to form an opening to expose the upper surface of the connecting layer; and forming and refluxing solder ball bumps on the connecting layer. The wafer-level packaging method improves the electrical performance and reliability of wafer-level packaging and is suitable for the wafer-level packaging of chips with dense pad spacing and multiple output functions.

Description

technical field [0001] The invention relates to the field of semiconductor device packaging, in particular to a method for forming a wafer level chip scale package (WaferLevel chip Scale Package, WLCSP). Background technique [0002] In recent years, since the microcircuit manufacturing of chips is developing toward high integration, the chip packaging also needs to develop in the direction of high power, high density, thinness and miniaturization. Chip packaging means that after the chip is manufactured, the chip is wrapped in plastic or ceramic materials to protect the chip from external moisture and mechanical damage. The main functions of the chip package are power distribution, signal distribution, heat dissipation and protection support. [0003] Since today's electronic products are required to be light, thin, small and highly integrated, the fabrication of integrated circuits will be miniaturized, resulting in an increase in the number of logic circuits contained in...

AI Technical Summary

Problems solved by technology

[0012] In the process of forming wafer-level chip size packaging in the prior art, since the solder bump material is in direct contact with the metal wetting layer, the copper in the metal wetting layer easily diffuses into the tin of the solder bump to form a copper-tin alloy, which affects the welding quality

At the same time, before the solder is formed on the metal wetting layer, the exposed wetting layer is easily oxidized, which reduces the performance and reliability of the subsequently formed solder bumps

On the other hand, during the formation of solder bumps, the solder is easy to drip and affect the reliability of the product, especially for products with dense metal pads, the problem of short circuit between solder bumps is more likely to occur

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