Method and device for testing data valid window of double data rate-3 (DDR3)

Abstract

The invention provides a method for testing a data valid window of double data rate-3 (DDR3). The method comprises the following steps of: calculating the size of the data valid window of the DDR3 and then setting the phase of a read data sampling clock according to the size of the window. By the method for testing the data valid window of the DDR3, the size of the data valid window can be tested by the method and a device for testing the data valid window of the DDR3 after hardware of a DDR3 memory is designed; then the position of a read clock sampling point is directly set according to the size of the window obtained by the test in the design of a DDR3 controller; therefore, the hardware design efficiency is improved, and the difficulty in the layout and the wiring of a printed circuit board (PCB) are reduced.

Description

technical field [0001] The invention relates to the field of DDR3 memory controllers, in particular to a method and device for testing the effective window of DDR3 data. Background technique [0002] In the DDR3 hardware design, due to differences in PCB traces, the timing at which the clock arrives at each data line is not consistent, which may lead to deviations when the same clock samples each data line. When designing the DDR3 controller with fpga, the phase relationship between the sampling clock and data is adjusted through the delay module of fpga to keep the clock and data line aligned. Due to the large number of data lines, it takes a lot of logic resources for phase alignment and data valid window search, but in the case of fpga logic resource shortage, there will be a problem that the design timing cannot meet the requirements for multiple data valid window search . [0003] In the patent No. ZL200780041136.5, titled "Read Alignment Implementation for DDR3 Appli...

AI Technical Summary

Problems solved by technology

However, using this method will occupy more fpga logic resources. In the case of a large fpga project and tight logic resources, it will lead to a shortage of logic resources, which in turn will cause difficulties in layout and routing, and difficult to meet the project timing.

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