Method and device for digital predistortion processing

Abstract

The invention provides a method and a device for digital predistortion processing, wherein the method includes the steps that: (A) the amplitude of an input signal x(n) is acquired, and the processed signal is time-division multiplexed into D channels of signals; predistortion parameters corresponding to the D channels of signals are respectively acquired; while the step A is executed, step B is executed: the input signal x(n) is delayed for time T and then time-division multiplexed into D channels of signals, wherein T is delay time which is generated when the amplitude and the predistortionparameters are acquired in the step A; (C) after the D channels of predistortion parameters generated in the step A and the D channels of signals generated in the step B are multiplied and accumulated in parallel, a signal y(n) is outputted, wherein D is an integer larger than 1. The invention can save more multiplier resources, reduce the difficulty of wiring and reduce the delay of predistortion processing.

Description

technical field [0001] The invention relates to the technical field of mobile communication, in particular to a method and device for digital predistortion processing. Background technique [0002] Linear modulation schemes are often required in mobile communication systems, in which linear power amplifiers (PAs) can be used, but their efficiency is low, and the frequency components emerging in high-efficiency nonlinear PAs will interfere with adjacent channels. In order to meet high efficiency And to overcome the demand of nonlinear effects, the adaptive digital predistortion (PDP) technology is proposed. The core idea of ​​the digital pre-distortion technology is to generate an "inverse" nonlinear compensation for the nonlinear PA to compensate the distortion caused by the nonlinear PA. [0003] figure 1 The schematic structure diagram of the device for digital pre-distortion processing, such as figure 1 As shown, the digital pre-distortion device mainly includes: a del...

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Problems solved by technology

In other words, the input signal x(n) needs to be serially processed by M-level multiplication and accumulation. Since each level needs to be delayed by 4 clock cycles, then the M-level needs to be delayed by 4M clock cycles, which is a long delay; In addition, since each level of processing requires a multiplication unit to multiply complex numbers, that is, x(n-m) and LUT m (|x(n-m)|) are all complex numbers and require 4 multipliers, so M-level requires 4M multipliers. Therefore, the multiplier consumes a lot of resources, which makes layout and wiring more difficult.

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