Matrix processor as well as instruction set and embedded system thereof
A processor and processor core technology, applied in the field of processors, can solve problems such as large hardware resource requirements, limited efficiency of hardware modules, and poor flexibility
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[0057] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0058] In order to enable the matrix processor instruction set to perform matrix calculations and realize complete algorithmic operations and control, the instruction set of the matrix processor should have six parts: L / S and move instructions, jump instructions, floating-point operation instructions, and mathematical functions instruction, single instruction multiple data (SIMD) instruction, matrix operation instruction.
[0059] According to actual needs, the specific instructions realized are: (1) L / S and movement instructions, including: LM, SM, LMR, SMR, MOV; (2) Jump instructions, including: JMP, JL, B, BL; ( 3) Floating-point arithmetic instructions, including: FABV, FCMP, FCMPZ, FCPY, FNEG, FADD, FSUB, FMUL, FDIV, FSQRT, FNMUL, FMAC, FMSB, NOP; (4) Mathematical function instructions, including: FSINF, FCOSF, FTANF, FARCSINF, FARCCOSF...
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