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Multi-circle arranged IC (integrated circuit) chip packaging member and producing method thereof

A technology of chip package and production method, which is applied in the direction of electrical components, electric solid devices, semiconductor devices, etc., can solve the problems that cannot satisfy ultra-thin package products, cannot meet high density, affect high-frequency applications, etc., and achieve signal transmission Fast, good thermal performance, short heat conduction distance

Active Publication Date: 2011-10-19
TIANSHUI HUATIAN TECH +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The current four-sided flat no-lead package cannot meet the needs of high-density, multi-I / O packaging due to fewer pins, that is, fewer I / Os. At the same time, the bonding wire is long, which affects high-frequency applications.
Moreover, the general thickness of QFN is controlled at 0.82 mm to 1.0 mm, which cannot meet the needs of ultra-thin packaging products.

Method used

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  • Multi-circle arranged IC (integrated circuit) chip packaging member and producing method thereof
  • Multi-circle arranged IC (integrated circuit) chip packaging member and producing method thereof
  • Multi-circle arranged IC (integrated circuit) chip packaging member and producing method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0054] (1), wafer thinning thickness 250μm

[0055] Coarse grinding thickness range, from original wafer to final thickness + adhesive film thickness + 50 μm, rough grinding speed 5 μm / s; fine grinding thickness range, from final thickness + adhesive film thickness + 50 μm to final wafer thickness + adhesive film thickness , Grinding speed: 0.4μm / s, wafer thinning method ordinary QFN thinning, 6-inch to 8-inch wafer VG-502MKⅡ8B automatic thinning machine, 8-inch to 12-inch wafer adopts PG300RM / TCN;

[0056] (2), scribing

[0057] Wafers up to 8 inches use DISC3350 or double-knife dicing machines, and wafers from 8 inches to 12 inches use A-WD-300TXB dicing machines. Application of anti-fragmentation and anti-crack scribing software control technology, the scribing speed is controlled at ≤10mm / s;

[0058] (3), single chip flip chip and reflow soldering

[0059] Single-chip flip-chip bonding, using IC chip 3 with bumps, flip-chip bonding is performed on a carrier frame with a...

Embodiment 2

[0075] (1), wafer thinning thickness 250μm

[0076] Coarse grinding thickness range, from original wafer to final thickness + adhesive film thickness + 50μm, rough grinding speed 2μm / s; fine grinding thickness range, from final thickness + adhesive film thickness + 50μm to final wafer thickness + adhesive film thickness , Grinding speed: 0.9μm / s, ordinary QFN thinning method for wafer thinning, VG-502MKⅡ8B automatic thinning machine for 6-inch to 8-inch wafers, PG300RM / TCN for 8-inch to 12-inch wafers;

[0077] (2) Scribing

[0078] With embodiment 1;

[0079] (3), single chip flip chip and reflow soldering

[0080] With embodiment 1;

[0081] (4), bottom filling

[0082] Choose a material with a low thermal expansion coefficient, heat the underfill to 80°C, use vacuum technology to underfill the bumps 4 and the pins in the frame, and finally bake the finished product after the underfill in a QFN general-purpose baking oven Bake for about 15 minutes;

[0083] (5)~(7)

...

Embodiment 3

[0092] (1)~(7)

[0093] With embodiment 1;

[0094] (8), separate pins

[0095] The pins are separated from each other by laser cutting method, and the cutting depth is 0.13μm;

[0096] (9), electroplating

[0097] The electroplating is the same as that of ordinary QFN packages, and the electroless plating system is directly plated with 7μm pure tin, and the baking conditions and methods after electroless plating are the same as those of ordinary QFN packages after electroplating;

[0098] (10), cutting and separating products

[0099] With embodiment 1.

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Abstract

The invention relates to a multi-circle arranged IC (integrated circuit) chip packaging member, which comprises a lead frame, inner pins, an IC chip and a plastic package body. The multi-circle arranged IC chip packaging member is characterized in that the lead frame is provided with a load; the inner pins of the lead frame are arranged around the lead frame in circles; the IC chip is provided with convex points; and the convex points are connected to the inner pins. Compared with a single-row lead frame with a same area, the multi-circle arranged IC chip packaging member has the advantage ofincreasing the number of the pins of the multi-circle arranged IC chip packaging member by over 40%; the pins can be connected with the lead frame without bonding wires; and the structure is simple and reasonable. In addition, as the heat conducting distance is short, the multi-circle arranged IC chip packaging member has better thermal property; as the convex points are in direct contact with the lead frame (a substrate, the chip), the inductance and the capacitance welded inside a circuit are reduced, the signal transmission speed is high, the distortion is little, and excellent electrical property is obtained; and the thickness and the weight of a package are reduced, thus reeling and disconnecting of a bonding wire are avoided, and the yield and the reliability for testing are improved.

Description

technical field [0001] The invention relates to the technical field of electronic information automation component manufacturing, in particular to four-sided flat leadless IC chip packaging, specifically a multi-circle arrangement IC chip package, and the invention also includes a production method of the package. Background technique [0002] In recent years, with the rapid development of portable electronic components in the field of mobile communications and mobile computers, small packaging and high-density assembly technology has been greatly developed; at the same time, a series of strict requirements have been put forward for small packaging technology, such as requirements Package dimensions should be kept as small as possible, especially if the package height is less than 1 mm. The reliability of the connection after packaging is improved as much as possible, which is suitable for lead-free soldering and effectively reduces costs. [0003] The integrated circuit pa...

Claims

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Application Information

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IPC IPC(8): H01L23/495H01L21/60
CPCH01L2224/16245
Inventor 朱文辉慕蔚李习周郭小伟
Owner TIANSHUI HUATIAN TECH
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