Current delay circuit

A delay circuit and current technology, applied in the direction of electrical components, adjusting electrical variables, DC power input to DC power output, etc., can solve the problems of delay change, sacrifice area, unfavorable chip integration, etc., to achieve stable delay, The effect of small mirror current error

Inactive Publication Date: 2011-07-20
ZHEJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

RC circuits generally use ordinary passive resistors or ordinary active resistors. If the required delay is large, ordinary resistors will inevitably sacrifice area, which is not conducive to integration on the chip, and ordinary active resistors will change with the change of external voltage. changes, so the delay will vary with the input current and supply voltage

Method used

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Embodiment Construction

[0010] refer to figure 1 As shown, the current delay circuit of the present invention includes five PMOS transistors (PM1, PM2, PM3, PM4, PM5), five NMOS transistors (NM1, NM2, NM3, NM4, NM5) and a current source I b . Among them, the current input terminal I in The drain of the NMOS transistor NM4, the gate of the NMOS transistor NM1 and the gate of the NMOS transistor NM2 are respectively connected, the gate of the NMOS transistor NM4 is connected to the gate of the NMOS transistor NM3 and the bias voltage Bias2 is connected, and the source of the NMOS transistor NM4 is connected to The drain of the NMOS transistor NM1, the source of the NMOS transistor NM1 are grounded, the source of the NMOS transistor NM2 is grounded, the drain of the NMOS transistor NM2 is connected to the source of the NMOS transistor NM3, and the drains of the NMOS transistor NM3 are respectively connected to the drain of the PMOS transistor PM3 pole, the gate of PMOS transistor PM1, the source of PM...

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PUM

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Abstract

The invention discloses a current delay circuit. The current delay circuit realizes delay by using a basic resistance-capacitance (RC) circuit of which a resistor R is realized by adopting a P-channel metal oxide semiconductor (PMOS) transistor, controls the source and gate voltages of the PMOS transistor by a voltage following circuit, stabilizes a resistance value of the PMOS transistor and reduces relationships between the resistance values and the source voltages, thereby stabilizing delay time. The current delay circuit is relatively less influenced by the magnitude of input current and the change of power voltage.

Description

technical field [0001] The invention relates to a current mode circuit, in particular to a current delay circuit. Background technique [0002] The current delay circuit currently used in China generally converts the current signal into a voltage signal, and delays the voltage signal through an RC delay circuit, and finally converts it back to the current signal. RC circuits generally use ordinary passive resistors or ordinary active resistors. If the required delay is large, ordinary resistors will inevitably sacrifice area, which is not conducive to integration on the chip, and ordinary active resistors will change with the change of external voltage. Changes, so the delay will vary with the input current and supply voltage. Contents of the invention [0003] The object of the present invention is to provide a current delay circuit which is less affected by the input current and power supply voltage in view of the deficiencies in the prior art. [0004] The purpose of ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H02M3/155
Inventor 沈海斌周祺李袁鑫张雷雷
Owner ZHEJIANG UNIV
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