Passivation layer dry etching method

Abstract

The invention discloses a passivation layer dry etching method. The method comprises the following steps: depositing a second passivation layer and a first passivation layer above an aluminum gasket at the surface of a silicon wafer, wherein the second passivation layer is positioned below the first passivation layer; etching the first passivation layer and the second passivation layer through plasma containing argon Ar; and stopping using Ar and continuing to etching the second passivation layer when the thickness of the second passivation layer is reduced to a pre-set thickness. Through theinvention, the PID is reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a passivation layer dry etching method. Background technique [0002] Etching refers to the selective removal of interconnection materials deposited on the surface of silicon wafers to form circuit patterns generated by photolithography. There are two types of etching processes: dry etching and wet etching. Dry etching is the plasma generated by exposing the surface of the silicon wafer to the gaseous state. The plasma passes through the window opened in the photoresist and reacts physically and / or chemically with the silicon wafer, thereby removing the exposed surface material. [0003] In the metallization process of semiconductor manufacturing, in order to increase the corrosion resistance of interconnect metals such as aluminum, two passivation layers are usually added above the aluminum pad, called the first passivation layer and the second passivation l...

AI Technical Summary

Problems solved by technology

The second passivation layer etching is considered to be the root cause of the PID phenomenon, because the plasma will act on the aluminum pad during the second passivation layer etching process, and will be transmitted to the gate oxide through the copper interconnection line in the front layer of the aluminum pad. layer, causing damage to the gate oxide layer, which increases the leakage current of the gate oxide layer

The disadvantage of the former is: the reduction of plasma energy will reduce the etching uniformity of the entire silicon wafer

The disadvantage of the latter is that although increasing the thickness of the gate oxide layer of the source and drain will increase the protection of the source and drain, the increase in the thickness of the gate oxide layer will increase the turn-on voltage and current, making normal operation Does not work properly under voltage

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