General packing method for FPGA (field programmable gate array) configurable logical block (CLB)

Abstract

The invention belongs to the technical field of electronics, in particular to a general packing method for an FPGA (field programmable gate array) configurable logical block (CLB). The method comprises the following steps: configuring and describing chips of the FPGA CLB as a series of directed simple graphs for constraining a satisfaction problem picture matching method; and then identifying a logical function sub-circuit supported by the chip from a user circuit by using the constraint satisfaction problem picture matching method, and packing. According to the invention, only if a library file which describes a target FPGA logical function circuit is pre-defined, the FPGA chips of different structures, such as various functional configurations of a quick carry chain, a distribution type memory, a shift register, an LUT5 (local user terminal 5), an LUT6 (local user terminal 6) and the like can be packed, thereby effectively improving the utilization rate of the logical resources of the chips, and improving the time sequence performance of the circuit. According to the invention, the circuit is optimized according to the appointed requirements, and the mapping of various modularized circuits is realized, thus the method has significant application in system architecture designs and reconfigurable systems.

Description

technical field [0001] The invention belongs to the electronic design automation (Electronic Design Automation, EDA) technical field, and specifically relates to a general packing method for programmable logic blocks in a Field Programmable Gate Array (FPGA, Field Programmable Gate Array). Background technique [0002] The chip structure of field programmable gate array includes programmable logic block (Configurable Logic Block, CLB), programmable input and output (Input Output Block, IOB) and programmable interconnection, with circuit function reconfigurable, short development cycle, design Low cost and other advantages, so it has a wide range of applications in the fields of national defense weapons and equipment, civil communications, automotive electronics and medical treatment. The FPGA software design process mainly includes: logic synthesis, process mapping, packing, placement and routing. Among them, packing is to divide the logic circuit after process mapping acco...

AI Technical Summary

Problems solved by technology

Literature [4] proposed a boxing method FDUMap for Xilinx's early XC3000 and XC4000 series chips, but it still cannot handle relatively complex functional configurations such as fast carry chains.

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