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Multi-core processor

A processor and multi-core technology, applied in the combination of various digital computers, etc., can solve the problems of limited expansion capability and limited chip power consumption, etc., and achieve the effect of easy expansion

Inactive Publication Date: 2010-11-10
HUNAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The method of improving digital signal processing capability by increasing the main frequency is limited by chip power consumption, heat dissipation and manufacturing process, and the expansion capability is limited

Method used

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Embodiment 1

[0034] figure 1 It includes multiple processor sets 1. The processor set includes a master processor 2 and a number of slave processors 3. The master processor and the slave processor and the slave processor and the slave processor are connected by a local bus 4. The processor sets and the processor sets and the debugging configuration unit are connected by the global bus 5 and the switching unit (SWITCH) 6. Some peripherals or hardware acceleration units may be integrated on the multi-core processor. figure 1 Not shown in, these peripherals or hardware acceleration units can also be connected to the debug configuration unit and the processor assembly through the global bus 5.

[0035] The master processor 2 controls the instructions and data executed by the slave processor 3. The slave processor may have no program memory and instruction fetching unit. The master processor sends an ultra-long instruction word to the slave processor 3 via the instruction bus in the local bus 4. Th...

Embodiment 2

[0056] figure 1 The mid-global bus 5 can not only transmit multipoint-to-multipoint data communication between the processor sets, but also transmit configuration, debugging, and tracking control information between the debugging configuration unit and the processor sets. The multi-core processor system can work in two modes, debug mode and non-debug mode. Regardless of whether it is in debug mode or non-debug mode, before the multi-core processor starts to run code, the debug configuration unit 9 is responsible for configuring the program memory of the main processor in all the processor sets on the entire multi-core processor, that is, placing the need in the processor set The code executed in is loaded into the program memory of the main processor. At the same time, the debug configuration unit may also need to initialize the register files, data memory or other special registers of the master processor and the slave processor in the processor set.

[0057] After the multi-co...

Embodiment 3

[0071] according to figure 2 The bus setting mode shown in includes a global bus 5, a global bus switching unit 6 and a local bus 4. All slave processors 3-A,..., 3-D in a processor set 1-A work together under the control and coordination of the master processor 2-A to complete the task of single instruction multiple data or multiple instruction multiple data At the same time, different processor sets can handle different tasks. In order to increase the processing capacity of the multi-core processor, or to increase the number of slave processors in each processor set, the number of processor sets can also be increased. The increase in the number of slave processors in the processor set does not change the structure of the bus and the bus input and output ports of the master and slave processors. Increasing the number of processor sets does not change the structure of the global bus and the global bus switching unit, so the processor capability of the multi-core processor of ...

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Abstract

The invention provides a multi-core processor which comprises a plurality of processor sets and a debugging configuration unit, wherein the processor sets are in row distribution, each processor set comprises a main processor and a plurality of slave processors, and all the main processor and the slave processors are ultra-long instruction word processors; the number of the processor sets is M*N, and the M*N processor sets form M*N arrays of the processor sets; M*N exchange units are in one-to-one correspondence to the M*N processor sets; an exchange unit is arranged at each node of the M*N arrays; upper and lower or left and right adjacent exchange units as well as the processor sets and the corresponding exchange units are all connected through global buses; and the first row of exchange units in the M*N exchange units are all connected with the debugging configuration unit through the global buses. The invention can realize that a plurality of processors in each processor set can seamlessly cooperate.

Description

Technical field [0001] The present invention belongs to the field of computer and digital communication, and relates to a multi-core processor. All main processors and slave processors in the multi-core processor are ultra-long instruction word processors. technical background [0002] The rapid development of digital communication, especially wireless communication, puts forward higher and higher requirements on the ability of digital signal processing. The method of improving the digital signal processing capability by increasing the main frequency is limited by the power consumption of the chip, heat dissipation and manufacturing technology, and limited expansion capability. Very long instruction word (VLIW) and multi-core processor architecture can well expand the capabilities of digital signal processors. [0003] We know that a parallel computer or an ultra-long computer uses a network to connect some general-purpose processors or computers to provide powerful processor capa...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/17
Inventor 陈荣吴桂清王卫平
Owner HUNAN UNIV
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