Slot filling method in multilayer integrated circuit

A filling method and integrated circuit technology, which is applied in the manufacture of circuits, electrical components, semiconductors/solid-state devices, etc., and can solve problems such as inability to remove photoresist and pollution of photoresist processes

Active Publication Date: 2010-10-20
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Once the filling of the trench is not complete and the cavity inside the trench is connected to the outside world, the photoresist will remain in the cavity or the structure in which the cavity is connected to the outside world and cannot be removed, and the remaining photoresist will pollute the subsequent process

Method used

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  • Slot filling method in multilayer integrated circuit
  • Slot filling method in multilayer integrated circuit
  • Slot filling method in multilayer integrated circuit

Examples

Experimental program
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Effect test

Embodiment Construction

[0027] The filling method of groove in multilayer integrated circuit of the present invention comprises the steps:

[0028] At the beginning, the surface of the silicon wafer has just etched a groove 10, and a layer of silicon dioxide (not shown) is thermally oxidized on the surface of the silicon wafer with the groove 10. The thickness of this layer of silicon dioxide is 50 ~ between.

[0029] Step 1, see Figure 2a , deposit a layer of silicon dioxide on the surface of the silicon wafer with the trench 10, this layer of silicon dioxide is a pad layer 41, not doped with p-type or n-type impurities, with a thickness of 500~ between.

[0030] Step 2, see Figure 2b , and then deposit a layer of silicon dioxide doped with p-type or n-type impurities on the surface of the silicon wafer, with a thickness of 5000~ In between, this layer of silicon dioxide fills the trench 10 on the one hand, and serves as a material for the first layer of interlayer dielectric 42 on the oth...

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Abstract

The invention discloses a slot filling method in a multilayer integrated circuit. In the method, slots are etched on the surface of a silicone wafer, and a layer of silicon dioxide is grown by thermal oxidation, and then the following steps are carried out: firstly, depositing a layer of silicon dioxide on the surface of the silicon wafer with the slots, wherein the layer of the silicon dioxide is a laying layer; secondly, depositing a layer of silicon dioxide mixed with p type or n type impurities on the laying layer, wherein the silicon dioxide mixed with the impurities fills the slots and is the material of the interlayer media of the first layer; and thirdly, carrying out planarization treatment on the silicon dioxide on the surface of the silicon wafer by a chemical mechanical polishing process until the required thickness of the interlayer media of the first layer is met. In the invention, the filling of the slots and the preparation of ILD-1 are skillfully integrated, and the material of the ILD-1 is determined as the silicon dioxide mixed with the impurities simultaneously. The silicon dioxide mixed with the impurities has good fluidity, and therefore, the requirements for filling deep slots with different widths can be completely met.

Description

technical field [0001] The invention relates to a manufacturing process of a semiconductor integrated circuit. Background technique [0002] Modern semiconductor integrated circuits adopt a multi-layer structure (at least two layers), with silicon at the bottom, one or more layers of metal on top of the silicon, and interlayer dielectrics between each layer of metal and between the first layer of metal and silicon. (ILD). [0003] In the underlying silicon manufacturing process, it is often necessary to fill the trenches with an isolation dielectric (such as silicon dioxide). The Shallow Trench Isolation (STI) process is a common trench filling method, but it is only suitable for shallow trenches (depth below 1 μm). For deep trenches (with a depth between 1 μm and 10 μm), multiple filling methods are usually used, and the specific steps are as follows: [0004] At the beginning, the surface of the silicon wafer has just etched a groove 10, and a layer of silicon dioxide (...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/762H01L21/316H01L21/3105H01L21/311
Inventor 陈华伦陈雄斌陈瑜熊涛罗啸
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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