High-voltage LDMOS device

Abstract

The invention discloses a high-voltage LDMOS device. The high-voltage LDMOS device comprises a grid (22) and a drain (23), wherein the drain (23) is arranged in a low-voltage N well (132) and the low-voltage N well (132) is arranged in a high-voltage N well (122); a part, above the high-voltage N well (122), between the grid (22) and the drain (23) is provided with silicon oxide (161); polycrystalline silicon (171) is arranged above the silicon oxide (161); and the two sidewalls of each of the silicon oxide (161) and the polycrystalline silicon (171) are provided with a silicon nitride sidewall (18) respectively. On one hand, the high-voltage LDMOS device can avoid the poor hot carrier effect and the Snapback breakdown of the device caused by a 'bird beak' structure of the conventional high-voltage LDMOS device; and on the other hand, 'field plate effect' can be achieved and electric field strength in the vicinity of a PN junction of the drain (23) is reduced, so that high breakdown voltage can be satisfied.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit structure, in particular to a MOS transistor. Background technique [0002] With the continuous development of semiconductor technology, the application of high-voltage LDMOS (Lateral Diffuse MOS Transistor) devices is becoming more and more extensive. At the same time, higher requirements are placed on the performance of high-voltage LDMOS devices. The problem of energy consumption has attracted more and more attention. [0003] see figure 1 , the high voltage LDMOS device includes an N-type buried layer 10 and an N-type epitaxial layer 11 . The N-type epitaxial layer 11 includes a high-voltage P-well 121 and a high-voltage N-well 122 , and also includes a low-voltage P-well 131 and a low-voltage N-well 132 . The field oxide layer 14 is outside the P-type active region 152, in the middle of the P-type active region 152 and the N-type active region 151 in the low-voltage P well 131, in the ...

AI Technical Summary

Problems solved by technology

However, the field oxide layer 14 used to isolate the gate 21 and the drain 23 in the middle of the high-voltage N well 122 has a very strong electric field at the edge 141 of its "bird beak", and the electron holes generated by the collision The pair also increases gradually, the leakage current I flowing to the substrate sub Gradually becomes larger, resulting in worse hot carrier effect (hot carrier effect)

At the same time, the leakage current I flowing to the substrate sub It will cause the parasitic NPN transistor to turn on, causing the Snapback breakdown of the device

Images