Sigma-Delta modulation circuit and method as well as corresponding phase-locked loop

Abstract

The invention discloses Sigma-Delta modulation circuit and method as well as a corresponding phase-locked loop. The Sigma-Delta modulation is realized by utilizing the feedback of quantization noise so as to flexibly select output bits when selecting quantization output. The Sigma-Delta modulation circuit comprises a first summator, a quantizer, a subtracter, a plurality of quantization noise delay circuits and a second summator, wherein the first summator receives a score input signal and a feedback signal, generates and outputs a sum signal; the quantizer receives a unit delay signal of the sum signal generated by the first summator and generates an integer output signal after the unit delay unit is quantized; the subtracter receives the unit delay signal of the sum signal generated by the first summator and the integer output signal generated by the quantizer, subtracts the integer output signal from the unit delay signal of the sum signal, then generates and outputs the quantization noise; the plurality of quantization noise delay circuits respectively output the quantization noise after being delayed; and the second summator receives outputs of the plurality of quantization noise delay circuits, generates a feedback signal after the outputs are summed and provides the feedback signal for the first summator.

Description

technical field [0001] The present invention relates to phase-locked loops (PLLs), and more particularly to sigma-delta modulators applied to phase-locked loops. Background technique [0002] Phase-locked loop (PLL) is a technology that utilizes the principle of feedback control to realize frequency and phase synchronization. It is widely used in many fields such as wireless communication, digital TV, and broadcasting. A basic phase-locked loop often includes a phase comparator (PFD), a low-pass filter (LPF) and a voltage-controlled oscillator (VCO). In practical applications, a frequency divider (Divider) is often set on the feedback loop to perform frequency division to generate a feedback signal. [0003] For details, please refer to figure 1 , which shows a structural block diagram of a common fractional frequency division phase-locked loop (FNPLL). As shown in the figure, the phase-locked loop includes a phase comparator (PFD) 10, a charge pump (Charge-Pump) 20, a lo...

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Problems solved by technology

However, the form of data processed by the MASH structure is bit by bit. This sigma-delta modulation form that only processes 1 bit at a time is relatively stable, but it lacks flexibility in the selection of the number of bits of the output result.

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