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Method for preventing cavities from generating in deep groove insulation technology

A process and void technology, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as reducing insulation performance, and achieve the effect of ensuring insulation performance, eliminating sharp corners, and avoiding voids

Inactive Publication Date: 2010-05-19
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the prior art, due to the stress matching problem between the polysilicon insulating material used in large quantities and the substrate silicon material, it is necessary to use an etching process to remove the polysilicon insulating material in the shallow trench, and then combine silicon oxide deposition and chemical mechanical polishing to complete the shallow trench. Trench structure manufacturing, in addition, because the trench etching is very easy to form sharp corners, the sharp corners will be first joined in the subsequent deposition process, resulting in a large number of voids in the trench, thereby reducing the insulation performance

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  • Method for preventing cavities from generating in deep groove insulation technology
  • Method for preventing cavities from generating in deep groove insulation technology
  • Method for preventing cavities from generating in deep groove insulation technology

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Embodiment Construction

[0015] The specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0016] First, please refer to Figure 7 , Figure 7 It is a process flow diagram of a method for preventing voids in the deep trench insulation process of the present invention. As shown in the figure, the present invention includes the following steps:

[0017] Step 31: Form an active region protection layer on the semiconductor substrate. In actual operation, an oxide layer, such as a silicon oxide layer, is deposited on the substrate silicon first, and then a silicon nitride layer is deposited on the oxide layer. The substrate described in the invention is a substrate on which an oxide layer has been deposited on a silicon wafer;

[0018] Step 32: Etching the active region protection layer and the semiconductor substrate to form deep trenches, generally using silicon nitride as a hard mask, and defining steep grooves on the semiconduc...

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Abstract

The invention provides a method for preventing cavities from generating in deep groove insulation technology, which comprises the following steps: forming an source region protective layer on a semiconductor substrate; etching the source region protective layer and the semiconductor substrate to form a deep groove; etching the source region protective layer and the semiconductor substrate to form a shallow groove communicated with the deep groove; adopting a high temperature oxidation technology on the edge of the deep groove and the edge of the shallow groove; carrying out etching by the wet method to remove the silicon oxide formed by the high temperature oxidation technology, and precipitating an insulating medium in the deep groove and the shallow groove; carrying out the chemical machinery grinding to flatten the surface of the shallow groove. The method of the invention enables the edges and corners of the grooves to be smooth, thereby avoiding large quantities of cavities in the groove and ensuring the insulating property of the groove.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing technology, in particular to a method for preventing voids in deep trench insulation technology. Background technique [0002] In the process of semiconductor integrated circuits, the traditional isolation technology is self-aligned field oxidation isolation technology, that is, the active area is covered with a hard mask, the substrate silicon in the field area is exposed, and then the isolation area is oxidized by thermal oxidation. silicon. This method is simple, practical, and has a mature production process. The disadvantage is that a "bird's beak" area will be formed at the boundary of the active region. In practice, it is difficult to reduce the size of the "bird's beak" to less than 0.1 μm. Therefore, when the feature size of the microelectronics process is reduced to 0.25 μm, the field oxidation process is gradually replaced by the Shallow Trench Isolation Techno...

Claims

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Application Information

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IPC IPC(8): H01L21/762
Inventor 朱骏
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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